IDT82V2044E Integrated Device Technology, IDT82V2044E Datasheet - Page 52

• Manufacturer Part Number: IDT82V2044E
• Description: 4 Channel T1/j1/e1 Short Haul Liu
• Manufacturer: Integrated Device Technology

QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
5
ACCESS PORT
described in the IEEE 1149.1 standards.
ters plus a Test Access Port (TAP) controller. Control of the TAP is per-
formed through signals applied to the Test Mode Select (TMS) and Test
The IDT82V2044E supports the digital Boundary Scan Specification as
The boundary scan architecture consists of data and instruction regis-
IEEE STD 1149.1 JTAG TEST
TRST
TDI
TCK
TMS
parallel latched output
Digital output pins
(Test Access Port)
Controller
IDR (Device Identification Register)
TAP
BSR (Boundary Scan Register)
IR (Instruction Register)
BR (Bypass Register)
Figure-21 JTAG Architecture
Control<6:0>
Digital input pins
52
Clock (TCK) pins. Data is shifted into the registers via the Test Data Input
(TDI) pin, and shifted out of the registers via the Test Data Output (TDO)
pin. Both TDI and TDO are clocked at a rate determined by TCK.
ister), IDR (Device Identification Register), BR (Bypass Register) and IR
(Instruction Register). These will be described in the following pages. Refer
to for architecture.
The JTAG boundary scan registers include BSR (Boundary Scan Reg-
High Impedance Enable
Select
MUX
TEMPERATURE RANGES
INDUSTRIAL
TDO