FLLXT971A Intel, FLLXT971A Datasheet
FLLXT971A
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FLLXT971A Summary of contents
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... Intel 3.3V Dual-Speed Fast Ethernet PHY Transceiver The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A also provides a Low Voltage PECL (LVPECL) interface for use with 100BASE-FX fiber networks ...
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... Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ...
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Contents 1.0 Pin Assignments ..............................................................................................................................12 2.0 Signal Descriptions ..........................................................................................................................16 3.0 Functional Description.....................................................................................................................21 3.1 3.2 3.3 3.4 3.5 3.6 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 4 DataSheet U .com LXT971A 3.3 V Dual-Speed Fast ...
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LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver 3.7 3.8 3.9 3.10 4.0 Application Information.................................................................................................................. 48 4.1 4.2 4.3 5.0 Test Specifications .......................................................................................................................... 56 5.1 5.2 6.0 Register Definitions ........................................................................................................................ 71 7.0 Package Specifications.................................................................................................................... 88 8.0 Product Ordering Information......................................................................................................... 90 ...
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Figures ...
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LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver Tables ...
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Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 4 DataSheet U .com LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver Status Register #2 (Address 17) ........................................................................................74 Interrupt Enable Register (Address 18).............................................................................75 ...
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... Table 1 “LQFP Numeric Pin List” (replaced TEST1 and TEST0 with GND). Added note under Section 2.0, “Signal Descriptions”: “Intel recommends that all inputs and multi- function pins be tied to the inactive states and all outputs be left floating, if unused.” Modified SD/TP description in Table 3 “LXT971A Network Interface Signal Added Table note 2 ...
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Page N/A Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 4 DataSheet U .com LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver Revision 001 Revision Date: January 2001 Description Clock Requirements: Modified language under Clock Requirements ...
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LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver 10 4 DataSheet U .com Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 ...
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Figure 1. LXT971A Block Diagram ADDR<4:0> LED/CFG<3:1> Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 4 DataSheet U .com LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver RESET Management / Mode Select MDIO Register Set Logic MDC ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 1.0 Pin Assignments Figure 2. LXT971A 64-Ball PBGA Assignments 12 4 DataSheet U .com MDINT CRS TXD3 TXD0 REF B COL TXD2 TX_EN CLK/ RESET GND ...
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Figure 3. LXT971A 64-Pin LQFP Assignments Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 4 DataSheet U .com LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 1 REFCLK/ MDDIS 4 RESET 5 TXSLEW0 6 ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 1. LQFP Numeric Pin List Pin ...
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Table 1. LQFP Numeric Pin List (Continued) Pin Datasheet Document #: ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 2.0 Signal Descriptions Note: Intel recommends that all inputs and multi-function pins be tied to the inactive states and all outputs be left floating, if unused. Table 2. LXT971A MII Signal Descriptions PBGA Pin ...
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Table 2. LXT971A MII Signal Descriptions (Continued) PBGA Pin Type Column Coding Input Output Analog Open Drain Table 3. LXT971A Network Interface Signal Descriptions PBGA Pin# ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 4. LXT971A Miscellaneous Signal Descriptions PBGA Pin B7 Type Column Coding Input, O ...
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Table 5. LXT971A Power Supply Signal Descriptions PBGA Pin# A6 D4, E3 E4, F3 F4, C6, C3, G7, G8 E5, D5 G3, G4 Table 6. LXT971A JTAG Test Signal Descriptions PBGA Pin Type ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 8. LXT971A Pin Types and Modes Modes HWReset SFTPWRDN HWPWRDN ISOLATE SLEEP 1. A High Z (High impedance) or three-state determines when the device is drawing a current of less than 20 ...
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Functional Description 3.1 Introduction The LXT971A is a single-port Fast Ethernet 10/100 transceiver that supports 10 Mbps and 100 Mbps networks and complies with all applicable requirements of IEEE 802.3. The LXT971A directly drives either a 100BASE-TX line ...
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... Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT971A has an active internal termination and does not require external termination resistors. Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to page 18) allow the designer to match the output waveform to the magnetic characteristics ...
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Fault Detection and Reporting The LXT971A supports two fault detection and reporting mechanisms. “Remote Fault” refers to a MAC-to-MAC communication function that is essentially transparent to PHY layer devices used only during auto-negotiation, and is applicable ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver bit 26.11 through software control. Setting Register bit 26. through the MDC/MDIO interface sets the MII pins (RXD[0:3], RX_DV, RX_CLK, RX_ER, COL, CRS, and TX_CLK higher drive strength. 3.2.3 ...
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Figure 5. Management Interface Write Frame Structure MDC MDIO (Write) 3.2.3.1.3 MII Interrupts The LXT971A provides a single interrupt pin (MDINT). Interrupt logic is shown in LXT971A also provides two dedicated interrupt registers. Register 18 provides interrupt enable and ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 3.3 Operating Requirements 3.3.1 Power Requirements The LXT971A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and analog circuits require 3.3V supplies (VCCD and VCCA). These inputs may be supplied ...
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Hardware Control Mode In the Hardware Control Mode, LXT971A disables direct write operations to the MDIO registers via the MDIO Interface. On power-up or hardware reset the LXT971A reads the Hardware Control Interface pins and sets the MDIO ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 7. Initialization Sequence 3.4.3 Reduced Power Modes The LXT971A offers two power-down modes and a sleep mode. 3.4.3.1 Hardware Power Down The hardware power-down mode is controlled by the PWRDWN pin. When ...
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Software Power Down Software power-down control is provided by Register bit 0.11 in the Control Register (refer to Table 43 on page • The network port is shut down. • The MDIO registers remain accessible. 3.4.3.3 Sleep Mode ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 3.4.5 Hardware Configuration Settings The LXT971A provides a hardware option to set the initial device configuration. The hardware option uses the three LED driver pins. This provides three control bits, as listed in ...
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Establishing Link See Figure 9 3.5.1 Auto-Negotiation If not configured for forced operation, the LXT971A attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP) bursts. Each burst consists link pulses ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 9. Link Establishment Overview Auto-Negotiation 3.6 MII Operation The LXT971A device implements the Media Independent Interface (MII) as defined in the IEEE 802.3 standard. Separate channels are provided for transmitting data from ...
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Transmit Enable The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN after the last bit of the packet. 3.6.3 Receive Data Valid The LXT971A asserts RX_DV when it receives a ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 10. 10BASE-T Clocking Figure 11. 100BASE-X Clocking Figure 12. Link Down Clock Transition 3.6.7 Loopback The LXT971A provides two loopback functions, operational and test (see paths are shown DataSheet ...
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Operational Loopback Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16 Data transmitted by the MAC (TXData) is looped back on the receive side of the MII (RXData). Operational loopback is not ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 10. Carrier Sense, Loopback, and Collision Conditions Speed 100 Mbps 10 Mbps 1. Test Loopback is enabled when 0. 3.7 100 Mbps Operation 3.7.1 100BASE-X Network Operations During 100BASE-X operation, ...
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Figure 15. 100BASE-TX Data Path Standard Data Flow Scrambler Bypass Data Flow shown in soon as the LXT971A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD, ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 3.7.2 Collision Indication Figure 18 and remains asserted for the duration of the collision as shown in Figure 18. 100BASE-TX Transmission with No Errors TX_CLK TX_EN TXD<3:0> CRS COL Figure 19. 100BASE-TX Transmission ...
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In the receive direction, the PCS layer performs the opposite function, substituting two preamble nibbles for the SSD. 3.7.3.1.2 Dribble Bits The LXT971A handles dribbles bits in all modes. If one to four dribble bits are received, the nibble ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 11. 4B/5B Coding Code Type DATA IDLE CONTROL 1. The /I/ (Idle) code group is sent continuously between frames. 2. The /J/ and /K/ (SSD) code groups are always sent in pairs; ...
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Table 11. 4B/5B Coding (Continued) Code Type INVALID 1. The /I/ (Idle) code group is sent continuously between frames. 2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. 3. The /T/ and ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver • De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to appear somewhat shorter to the MAC than it actually is on the wire. • CRS de-assertion is ...
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Programmable Slew Rate Control The LXT971A device supports a slew rate mechanism whereby one of four pre-selected slew rates can be used. This allows the designer to optimize the output waveform to match the characteristics of the magnetics. ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 3.8.4 10BASE-T Link Integrity Test In 10BASE-T mode, the LXT971A always transmits link pulses. When the Link Integrity Test function is enabled (the normal configuration), it monitors the connection for link pulses. Once ...
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Register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex). 3.9.1.1 Monitoring Next Page Exchange The LXT971A offers an Alternate Next Page mode to simplify the next page exchange process. Normally, ...
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... Boundary Scan (JTAG1149.1) Functions LXT971A includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. The BSDL file is available by contacting your local sales office or by accessing the Intel website (www.intel.com). 3.10.1 Boundary Scan Interface This interface consists of five pins (TMS, TDI, TDO, TRST, and TCK) ...
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... Table 14. Device ID Register 31:28 Version XXXX 1. The JEDEC 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC (1111 1110), which becomes 111 1110. 2. See the LXT971A/972A Specification Update (document number 249354) for the current version of the Jedec continuation characters. ...
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... A cross-reference list of magnetic manufacturers and part numbers is available in Magnetic Manufacturers for Networking Product Applications (document number 248991) and is found on the Intel web site (www.Intel.com). Before committing to a specific component, contact the manufacturer for current product specifications and validate the magnetics for the specific application ...
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Figure 22. Typical Twisted-Pair Interface - Switch 1. Center-tap current may be supplied from 3.3 V VCCA as shown. Additional power savings 2. The 100 Ω transmit load termination resistor typically required is integrated in the 3. Magnetics without ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 23. Typical Twisted-Pair Interface - NIC 50 4 DataSheet U .com 270 pF 5% TPFIN 50Ω 1% 0.01 µF 50Ω 1% TPFIP 270 pF 5% TPFON LXT971A 2 0.1µF TPFOP VCCA 0.1µF ...
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Figure 24. Typical MII Interface Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 4 DataSheet U .com LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver TX_EN TX_ER TXD<3:0> TX_CLK RX_CLK RX_DV MAC LXT971A RX_ER RXD<3:0> CRS COL ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 4.3 The Fiber Interface The fiber interface consists of an LVPECL transmit and receive pair to an external fiber-optic transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers can be used ...
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Figure 25. Typical LXT971A-to-3.3 V Fiber Transceiver Interface Circuitry Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 4 DataSheet U .com LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver +3.3V +3.3V 16Ω 0.01µF − 0.1µ F 50Ω ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 26. Typical LXT971A-to-5 V Fiber Transceiver Interface Circuitry 54 4 DataSheet U .com +3.3V +3.3V 0.01µF 16Ω − 0.1µF 1.1kΩ 50Ω 50Ω 0.01µF TPFON 0.01µF TPFOP LXT971A 2 ON Semiconductor MC100LVEL92 SD/TP ...
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Figure 27. ON Semiconductor Triple PECL-to-LVPECL Translator Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 4 DataSheet U .com LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 0.01 µ Semiconductor 82Ω Vcc ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 5.0 Test Specifications Note: Table 17 through Table 40 specifications of the LXT971A. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in recommended operating conditions ...
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Table 19. Digital I/O Characteristics Input Low voltage Input High voltage Input current Output Low voltage Output High voltage 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 22. I/O Characteristics - LED/CFG Pins Input Low Voltage Input High Voltage Input Current Output Low Voltage Output High Voltage Table 23. I/O Characteristics – SD/TP Pin Fiber Mode (Register bit 16.0 ...
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Table 25. 100BASE-FX Transceiver Characteristics Peak differential output voltage (single ended) Signal rise/fall time Jitter (measured differentially) Peak differential input voltage Common mode input range 1. Typical values are at 25 °C and are for design aid only; not ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 28. LXT971A Thermal Characteristics Parameter Package Theta-JA Theta-JC Psi - DataSheet U .com LXT971ALC LXT971ALE x1 LQFP 1.4 64 LQFP ...
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Timing Diagrams Figure 28. 100BASE-TX Receive Timing - 4B Mode Table 29. 100BASE-TX Receive Timing Parameters - 4B Mode RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD<3:0>, RX_DV ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 29. 100BASE-TX Transmit Timing - 4B Mode Table 30. 100BASE-TX Transmit Timing Parameters TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted ...
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Figure 30. 100BASE-FX Receive Timing Table 31. 100BASE-FX Receive Timing Parameters RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD<3:0>, RX_DV Receive start of “J” to CRS asserted Receive start ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 31. 100BASE-FX Transmit Timing Table 32. 100BASE-FX Transmit Timing Parameters TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to ...
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Figure 32. 10BASE-T Receive Timing Table 33. 10BASE-T Receive Timing Parameters RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High TPFIP RXD out (Rx latency) CRS asserted to RXD, RX_DV, RX_ER asserted ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 33. 10BASE-T Transmit Timing TX_CLK TX_EN, TX_ER TPFO Table 34. 10BASE-T Transmit Timing Parameters TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS ...
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Figure 34. 10BASE-T Jabber and Unjabber Timing TX_EN Table 35. 10BASE-T Jabber and Unjabber Timing Parameters Maximum transmit time Unjab time 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 36. Auto-Negotiation and Fast Link Pulse Timing TPFOP Figure 37. Fast Link Pulse Timing TPFOP Table 37. Auto-Negotiation and Fast Link Pulse Timing Parameters Clock/Data pulse width Clock pulse to Data pulse ...
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Figure 38. MDIO Input Timing Figure 39. MDIO Output Timing Table 38. MDIO Timing Parameters MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, source by PHY MDC period ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 40. Power-Up Timing MDIO,etc Table 39. Power-Up Timing Parameters Voltage threshold Power Up delay 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject ...
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Register Definitions The LXT971A register set includes multiple 16-bit registers. listing. individual register definitions. Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 72 4 DataSheet U .com Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 ...
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Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 4 DataSheet U .com LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 73 ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 43. Control Register (Address 0) Bit 0.15 0.14 0.13 0.12 0.11 0.10 0.9 0.8 0.7 0.6 0.5:0 1. R/W = Read/Write RO = Read Only SC = Self Clearing 2. Default value ...
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Table 44. MII Status Register #1 (Address 1) Bit 1.15 1.14 1.13 1.12 1.11 1.10 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 Read Only LL = Latching Low LH = Latching High Datasheet ...
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... Organizationally Unique Identifier PHY ID Register #1 (address 2) = 0013 The Intel OUI is 00207B hex 1 Type Default RO 0013 hex 1 Type Default RO 011110 RO 001110 ...
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Table 47. Auto-Negotiation Advertisement Register (Address 4) Bit 4.15 4.14 4.13 4.12 4.11 4.10 4.9 4.8 4.7 4.6 4.5 4.4:0 1. R/W = Read/Write RO = Read Only 2. The default setting of Register bit 4.10 (PAUSE) is determined ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 48. Auto-Negotiation Link Partner Base Page Ability Register (Address 5) Bit 5.15 5.14 5.13 5.12 5.11 5.10 5.9 5.8 5.7 5.6 5.5 5.4 Read Only 78 4 DataSheet U ...
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Table 49. Auto-Negotiation Expansion (Address 6) Bit 6.15:6 6.5 6.4 6.3 6.2 6.1 6 Read Only LH = Latching High Table 50. Auto-Negotiation Next Page Transmit Register (Address 7) Bit 7.15 7.14 7.13 7.12 7.11 7.10:0 ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 51. Auto-Negotiation Link Partner Next Page Receive Register (Address 8) Bit 8.15 8.14 8.13 8.12 8.11 8.10 Read Only DataSheet U .com Name Description 1 = Link ...
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Table 52. Configuration Register (Address 16, Hex 10) Bit 16.15 16.14 16.13 16.12 16.11 16.10 16.9 16.8 16.7 16.6 16.5 16.4:3 16.2 16.1 16.0 1. R/W = Read /Write LHR = Latches High on Reset 2. The default value ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 53. Status Register #2 (Address 17) Bit 17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17:3 17:2 17:1 17 Read Only. R/W = Read/Write 82 ...
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Table 54. Interrupt Enable Register (Address 18) Bit 18.15:9 18.8 18.7 18.6 18.5 18.4 18.3 18.2 18.1 18.0 1. R/W = Read /Write Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 4 DataSheet U .com ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 55. Interrupt Status Register (Address 19, Hex 13) Bit 19.15:9 19.8 19.7 19.6 19.5 19.4 19.3 19.2 19.1 19.0 1. R/W = Read/Write Read Only Self Clearing. 84 ...
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Table 56. LED Configuration Register (Address 20, Hex 14) Bit 20.15:12 20.11:8 1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 56. LED Configuration Register (Address 20, Hex 14) (Continued) Bit 20.7:4 20.3:2 20.1 20.0 1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the ...
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Table 58. Transmit Control Register (Address 30) Bit 30.15:11 30.12 30.11:10 30.9:0 1. Values are relative approximations. Not guaranteed or production tested. 2. R/W = Read/Write Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 4 ...
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 7.0 Package Specifications Figure 43. PBGA Package Specification • Part Number - LXT971ABC Commercial Temperature Range (0ºC to +70ºC) • Part Number - LXT971ABE Extended Temperature Range (-40ºC to +85ºC) 0.20 (4X) 1.26 ...
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Figure 44. LXT971A LQFP Package Specifications Dim 11. 11. θ 3 θ 1. Basic Spacing between Centers Datasheet Document #: 249414 Revision #: ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 8.0 Product Ordering Information Table 59. Product Information DJLXT971ALC.A4 DJLXT971ALE.A4 FLLXT971ABC.A4 FLLXT971ABE.A4 Figure 45. Ordering Information - Sample DataSheet U .com Number Revision Qualification LXT 971A Tray MM Tape & Reel MM 834105 834916 835676 ...