FLLXT971A Intel, FLLXT971A Datasheet - Page 25

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

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4
3.2.3.2
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Figure 5. Management Interface Write Frame Structure
Figure 6. Interrupt Logic
3.2.3.1.3 MII Interrupts
The LXT971A provides a single interrupt pin (MDINT). Interrupt logic is shown in
LXT971A also provides two dedicated interrupt registers. Register 18 provides interrupt enable
and mask functions and Register 19 provides interrupt status. Setting Register bit 18.1 = 1, enables
the device to request interrupt via the MDINT pin. An active Low on this pin indicates a status
change on the LXT971A. Interrupts may be caused by four conditions:
Hardware Control Interface
The LXT971A provides a Hardware Control Interface for applications where the MDIO is not
desired. The Hardware Control Interface uses the three LED driver pins to set device configuration.
Refer to the Hardware Configuration Settings section on page 30 for additional
•
•
•
•
(Write)
MDIO
Even X Status Reg
MDC
Even X Mask Reg
Auto-negotiation complete
Speed status change
Duplex status change
Link status change
Force Interrupt
Idle
Preamble
32 "1"s
0
ST
1
0
Op Code
1
AND
A4
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
PHY Address
A3
A0
Interrupt Enable
Write
OR
R4
Register Address
R3
R0
1
NAND
Around
Turn
0
Interrupt Pin (MDINT)
D15
D14
Data
details.
D1
Figure
D0
6. The
Idle
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