IDT72V3642L10PF IDT, Integrated Device Technology Inc, IDT72V3642L10PF Datasheet - Page 19
IDT72V3642L10PF
Manufacturer Part Number
IDT72V3642L10PF
Description
IC FIFO SYNC 3.3V CMOS 120-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V3642L10PF.pdf
(29 pages)
Specifications of IDT72V3642L10PF
Function
Synchronous
Memory Size
72M (1M x 72)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V3642L10PF
800-1534
800-1534
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V3642L10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V3642L10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. t
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
B0 - B35
A0- A35
If the time between the rising CLKB edge and rising CLKA edge is less than t
cycle later than shown.
SKEW1
CLKB
CLKA
W/RA
W/RB
MBB
ORA
MBA
CSB
CSA
ENB
ENA
IRB
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
FIFO2 Empty
LOW
LOW
HIGH
LOW
LOW
LOW
Figure 10. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)
t
t
ENS2
ENS2
t
DS
W1
Old Data in FIFO2 Output Register
t
SKEW1
t
t
ENH
t
DH
ENH
(1)
t
CLKH
1
t
CLK
t
CLKL
SKEW1
TM
, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
t
CLKH
19
2
t
CLK
t
3
REF
t
A
t
CLKL
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
REF
t
ENH
W1
4660 drw 12