IDT72V3642L10PF IDT, Integrated Device Technology Inc, IDT72V3642L10PF Datasheet - Page 26

• Manufacturer Part Number: IDT72V3642L10PF
• Description: IC FIFO SYNC 3.3V CMOS 120-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3642L10PF

• Function: Synchronous
• Memory Size: 72M (1M x 72)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3642L10PF; 800-1534

NOTES:
1. t
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3622, 512 for the IDT72V3632, 1,024 for the IDT72V3642.
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
A0 - A35
B0 - B35
CLKB
CLKA
ENB
CLKA edge is less than t
AFB
ENA
SKEW2
CLKA
CLKB
W/RA
MBF1
W/RB
MBA
CSB
MBB
CSA
ENA
ENB
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
[D-(Y2+1)] Words in FIFO2
SKEW2
t
ENS2
, then AFB may transition HIGH one CLKB cycle later than shown.
t
Figure 19. Timing for AFB
EN
Figure 20. Timing for Mail1 Register and MBF1
FIFO1 Output Register
t
ENH
t
PAF
t
t
t
t
ENS1
ENS1
ENS2
ENS2
t
DS
W1
AFB
AFB
AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
AFB
t
MDV
t
t
t
t
DH
t
ENH
ENH
ENH
ENH
t
t
ENS2
PMF
TM
t
PMR
MBF1
MBF1
MBF1
MBF1 Flag (IDT Standard and FWFT Modes)
26
(D-Y2) Words in FIFO2
t
SKEW2
t
ENH
W1 (Remains valid in Mail1 Register after read)
(1)
1
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
ENH
t
2
PMF
t
PAF
t
DIS
4660 drw 21
4660 drw 22