UPD160040A NEC, UPD160040A Datasheet - Page 4

• Manufacturer Part Number: UPD160040A
• Description: 384-OUTPUT TFT-LCD SOURCE DRIVER
• Manufacturer: NEC

4. PIN FUNCTIONS
4
S
D
D
D
D
D
D
R,/L
STHR
STHL
CLK
STB
SRC
ORC
POL
Pin Symbol
1
00
10
20
30
40
50
to S
to D
to D
to D
to D
to D
to D
384
07
17
27
37
47
57
Driver
Port 1 display data
Port 2 display data
Shift direction control
Right shift start pulse
Left shift start pulse
Shift clock
Latch
Slew-rate control
Output resistance control
Polarity
Pin Name
Output
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Data Sheet S15918EJ1V0DS
The D/A converted 256-gray-scale analog voltage is output.
The display data is input with a width of 48 bits, viz., the gray scale data
(8 bits) by 6 dots (2 pixels).
D
The shift direction control pin of shift register. The shift directions of the
shift registers are as follows.
R,/L = H (right shift): STHR input
R,/L = L (left shift) : STHL input
These are the start pulse input/output pins when connected in cascade.
Loading of display data starts when a high level is read at the rising
edge of CLK.
At the rising edge of the 64th clock after the start pulse input, the start
pulse output reaches the high level, thus becoming the start pulse of
the next-level driver.
For right shift, STHR is input and STHL is output.
For left shift, STHL is input and STHR is output.
The shift clock input pin of shift register. The display data is loaded into
the data register at the rising edge.
When 66 clock pulses are input after input of the start pulse, input of
display data is halted automatically. The contents of the shift register
are cleared at the STB’s rising edge.
The contents of the data register are transferred to the latch circuit at
the rising edge. In addition, at the falling edge, the gray scale voltage is
supplied to the driver. It is necessary to ensure input of one pulse per
horizontal period.
SRC = H: High-slew-rate mode (large current consumption)
SRC = L: Low-slew-rate mode (small current consumption)
SRC is pulled up to the V
ORC = H: Low output resistance mode
ORC = L: High output resistance mode
ORC is pulled up to the V
POL = L: The S
POL = H: The S
S
of the POL signal is allowed the setup time (t
STB’s rising edge.
When it switches such as POL = H L or L H, all output pins are
output reset during STB = H. When it does not switch, all output pins
become Hi-Z (High impedance) during STB = H.
Refer to 7. RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL
AND OUTPUT WAVEFORM for details.
X0
2n 1
: LSB, D
indicates the odd output and S
output uses V
The S
X7
: MSB
2n 1
2n 1
2n
output uses V
output uses V
output uses V
8
-V
DD1
DD1
15
as the reference supply.
in the IC.
in the IC.
Description
0
-V
0
8
-V
-V
7
S
S
2n
7
15
as the reference supply.
384
1
as the reference supply. The S
indicates the even output. Input
as the reference supply.
S
384
S
1
POL–STB
STHR output
STHL output
www.DataSheet4U.com
) with respect to
PD160040A
(1/2)
2n