UPD160061A NEC, UPD160061A Datasheet
UPD160061A
Related parts for UPD160061A
UPD160061A Summary of contents
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... V SS2 rendered unnecessary. Also able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 65 MHz when driving at 2 ...
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BLOCK DIAGRAM STHR R,/L CLK STB POL21 POL22 SRC ...
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PIN CONFIGURATION (Copper foil surface: Face-up) µ ( PD160061AN-xxx: TCP (TAB package) / STHL ...
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... The display data is input with a width of 36 bits, viz., the gray scale data (6 bits dots (2 pixels LSB MSB X0 X5 These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. →S R,/ (right shift): STHR input STHL output 1 384 → ...
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Pin Symbol Pin Name I/O SRC High driving time Input control γ − -corrected power 0 9 supplies V Logic power supply − DD1 − V Driver power supply DD2 − V Logic ground SS1 − V ...
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... respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine-gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the compensated power supplies and Figure 5–1 shows the relationship between the driving voltages such as liquid-crystal driving voltages V ...
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... V ’ ’ Cautions1. There is no connection between V 2. The resistance ratio is a relative ratio in the case of setting the resistance minimum value to 1. γ - corrected Voltages and Ladder Resistors Ratio ’’ 11. ’ ...
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Figure 5–3. Relationship between Input Data and Output Voltage (POL21, POL22 = L) Output Voltage 1: V Output Voltage 2: 0.5 V Input V 00H 01H V V 02H V 03H V 04H V 05H V 06H V 07H V ...
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RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format : 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) (1) R,/ (Right shift) Output Data ...
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... CLK[1′]. Latch operation of display data is completed with the falling edge of the next CLK which loaded STB = H. Therefore, in order to complete latch operation of display data necessary to input at least 2 CLK in STB = H period. Besides, after loading STB=H to the timing of [1 necessary to continue inputting CLK. ...
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RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM When the STB is high level, all outputs became Hi-Z and the gray-scale voltage is output to the LCD in synchronization with the falling edge of STB. Therefore, high drive time of ...
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BIAS CURRENT CONTROL BY LPC AND HPC µ The PD160061A can control the bias current of the output amplifier in high drive period and low drive period. Bias Current LPC High H Middle H or open Normal L or ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25° Parameter Symbol Logic Part Supply Voltage V DD1 Driver Part Supply Voltage V DD2 Logic Part Input Voltage V I1 Driver Part Input Voltage V I2 Logic Part Output ...
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... The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 4. Refers to the current consumption per driver when cascades are connected under the assumption of XGA single-sided mounting (8 units). Switching Characteristics (T = – ...
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Timing Requirements (T = –10 to +75° Parameter Symbol Clock Pulse Width PW Clock Pulse High Period PW Clock Pulse Low Period PW Data Setup Time t SETUP1 Data Hold Time t HOLD1 Start Pulse Setup Time t ...
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SWITCHING CHARACTERISTICS WAVEFORM (R,/L= H) Unless otherwise specified, the input level is defined 0 0 DD1 IL DD1 Data Sheet S16041EJ2V0DS µ PD160061A www.DataSheet4U.com ...
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... RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the For more details, refer to the Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html). Please consult with our sales offices in case other mounting process is used case the mounting is done under different conditions. ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...