UPD160061A NEC, UPD160061A Datasheet - Page 11

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UPD160061A

Manufacturer Part Number
UPD160061A
Description
384-OUTPUT TFT-LCD SOURCE DRIVER
Manufacturer
NEC
Datasheet
8. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM
with the falling edge of STB.
setting. Be sure to avoid using such as extremely changing the CLK frequency (ex. CLK stop).
9. SRC AND HIGH DRIVE TIME
When the STB is high level, all outputs became Hi-Z and the gray-scale voltage is output to the LCD in synchronization
Therefore, high drive time of the output amplifier as below is determined by the CLK number of the required SRC pin
The
We recommend a thorough simulation of the output amplifier in advance when set the SRC pin.
µ
Inside bias current
PD160061A can control high drive time of the output amplifier by SRC pin logic (refer to below figure).
SRC = H or open (high drive time: standard mode): High drive time (PWhp) of the output amplifier is in 64 CLK
SRC = L (high drive time: long-term mode): High drive time (PWhp) of the output amplifier is in 128 CLK period
Vx (even output)
Vx (odd output)
Inside bias current
POL
STB
STB
CLK
Hi-Z
High drive time
V
V
0
5
- V
- V
Data Sheet S16041EJ2V0DS
4
9
from falling edge of the STB.
Hi-Z
High drive time
period from falling edge of the STB.
V
V
5
0
- V
- V
9
4
PWhp
Hi-Z
High drive time
V
V
5
0
- V
- V
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9
4
µ
PD160061A
11

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