UPD16602N NEC, UPD16602N Datasheet

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UPD16602N

Manufacturer Part Number
UPD16602N
Description
312-OUTPUT TFT-LCD FULL COLOR DRIVER
Manufacturer
NEC
Datasheet

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UPD16602N-056
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IBM
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UPD16602N-056
Manufacturer:
NEC
Quantity:
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Document No. S10671EJ1V0DS00 (1st edition)
Date Published August 1998 N CP(K)
Printed in Japan
high definition displays. The internal circuit consists of 12 channels (4
registers and 312 channels of sample & hold circuits (2 latch type).
the next line. The output voltage of the sample & hold circuits is as great as 10.5 V
output deviation of ±20 mV
processing circuit allows realization of a high definition 256-gray-scale-equivalent full color display without requiring line
inversion.
FEATURES
• 4
• High dynamic range (10.0 V
• High accuracy sample & hold circuits (output deviation; ±20 mV
• High-speed sampling frequency (for both analog and digital; f
• Low power control (reduction of output buffer bias current) function on chip
• Bi-directional data store function on chip
• Corresponding to high-density mounting (slim TCP)
ORDERING INFORMATION
PD16602N-
The PD16602 is a TFT-LCD source driver with full color display capability. It is ideal for 1024
Analog display signals are sampled in 12 channels simultaneously by the sample & hold circuits and they are output in
(operating power consumption; 82 mW
3 (RGB)-channel analog input allows display signal input wiring to be reduced.
Part Number
312-OUTPUT TFT-LCD FULL COLOR DRIVER
MAX
TCP
. Inputting analog display signals that been
P-PMIN.
V
DD2
Package
TYP.
DATA SHEET
= 11.0 V)
, V
DD2
12.5 V)
MOS INTEGRATED CIRCUIT
max.
MAX.
3) of analog input pins, 12 channels of 16-bit shift
20 MHz
, ±5.0 mV
-processed in the previous stage signal
MIN.
P-P
TYP.
)
and maintains high accuracy with an
)
PD16602
768 pixel (XGA) class
©
1998

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UPD16602N Summary of contents

Page 1

TFT-LCD FULL COLOR DRIVER The PD16602 is a TFT-LCD source driver with full color display capability ideal for 1024 high definition displays. The internal circuit consists of 12 channels (4 registers and 312 channels of sample & ...

Page 2

BLOCK DIAGRAM R/L CLK SPR 1 S PL/NL HS BIAS1 BIAS2 S 1 SAMPLE & HOLD + OUTPUT BUFFER CIRCUIT 1 D ...

Page 3

SAMPLE & HOLD + OUTPUT BUFFER CIRCUIT PL/NL S Sample and hold S + Output buffer circuit 5 ...

Page 4

PIN CONFIGURATION V SS2(A) V SS2(A) V SS2(C) V SS2(C) V DD2(A) V DD2(A) V DD2(D) V DD2(D) V DD1 V DD1 SDB RLB CLK SPL BIAS ...

Page 5

PIN DESCRIPTION Pin Symbol Pin Name Driver outputs 1 312 CLK Clock input Analog display signal inputs R/L Shift direction switching ...

Page 6

... V analog display signal input, and turned off in the reverse BIAS1,2 COM are connected in the diffusion layer, but also be sure to connect them with other ground wiring on the mount board, but connect it to SS2(C) DD2(D), ( pF, but when the time constant is smaller than ...

Page 7

FUNCTIONAL DESCRIPTION (1) Input Specification of the analog display signal ( 25, R/L = “H” or “L”) S/D PL/ 12n 12n H H (–) (+) L ...

Page 8

Sampling and hold timing (R/L S/D “L” (Dual Bank Arrangement) Line (N – 1) writing HS Note PL/NL Line (N – 1) (S/H) P (S/H) N Positive output 312 Hi-Z Note PL/NL H; input negative ...

Page 9

Relatonship with HS and PL/ HS-SETUP HS-HOLD PL/NL CLK SPR (SPL) Hi-Z Caution HS and PL/NL edges have no relationship with clock timing. Timing Item Symbol Horizontal synchronization t HS-SETUP setup time Horizontal synchronization t HS-HOLD ...

Page 10

Cascade timing R/L H (right shift) 0 CLK SPR SPL (Next stage SPR R/L ...

Page 11

ELECTRIC SPECIFICATION ABSOLUTE MAXIMUM RATINGS (T Item Logic supply voltage V Logic input voltage V Logic output voltage V Driver supply voltage V Display signal input voltage V Driver output voltage V Driver output current I O2 Operating temperature ...

Page 12

ELECTRICAL SPECIFICATIONS (T A Item Symbol High-level output voltage V OH Low-level output voltage V OL Input leakage current I iL Driver output current (black level) I OH11 Driver output current (white level) I OH12 Driver output current (white level) ...

Page 13

SWITCHING CHARACTERISTICS (T A Item Symbol Start pulse output delay tIme t PLH1 Driver output delay time t PHL2 t PHL3 t PLH2 t PLH3 Input capacitance Maximum clock frequency f max. TIMING REQUIREMENT ...

Page 14

SWITCHING CHARACTERISTICS (R/L Unless otherwise specified, the input levels are all set to 0 CLK CLK t SETUP SPR (SPL) SPL (SPR HS-SETUP PL/NL SPR (input) SPR (input refers to the ...

Page 15

... RECOMMENDED MOUNTING CONDITIONS When mounting this product, please make sure that the following recommended conditions are satisfied. For packaging methods and conditions other than those recommended below, please contact NEC sales personnel. Mounting Condition Mounting Method Thermocompression Soldering ACF (Adhesive Conductive Film) Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company ...

Page 16

... Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...

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