UPD16602N NEC, UPD16602N Datasheet - Page 5

• Manufacturer Part Number: UPD16602N
• Description: 312-OUTPUT TFT-LCD FULL COLOR DRIVER
• Manufacturer: NEC

3. PIN DESCRIPTION
Note Sample & hold operation and reset operation of the output buffer capacitance and V
S
CLK
D
D
D
R/L
SPR
SPL
PL/NL
S/D
HS
LPC
BIAS
BIAS
V
V
V
V
V
V
V
V
TEST
1
DD1
DD2(D)
DD2(A)
COM
SS1
SS2(D)
SS2(A)
SS2(C)
R0
G0
B0
to S
Note
to D
to D
to D
Pin Symbol
1
2
Note
312
by the PL/NL and HS logic.
R3
B3
G3
Driver outputs
Clock input
Analog display
signal inputs
Shift direction
switching input
Start pulse input/
output
Start pulse input/
output
Polarity inversion
input
Arrangement
switching input
Horizontal
synchronous input
Low power control
input
Bias voltage inputs
Logic power supply
Driver power supply
Driver power supply
Common power
supply
Logic ground
Driver ground
Driver ground
Driver ground
Test pin
Pin Name
Output pins for sampled analog image signals. When driven with V
11.5 V
This pin reads the start pulse at the rising of CLK and starts sampling of analog
display signals in 12 channels simultaneously. The active edges of CLK are all
rising edges.
Analog image signal input pins. Please input analog display signals by inverting the
polarity for each display line.
The shift direction of the shift register is as follows.
R/L = H (right shift) ;
R/L = L (left shift)
R/L = H (right shift) ;
R/L = L (left shift)
R/L = H (right shift) ;
R/L = L (left shift)
S/D = L; When PL/NL = H, Both odd number pin and even number pin samples
S/D = H; When PL/NL = H, Odd number pin samples negative analog display signals
S/D = H; Complying with one side arrangement dot inverting.
S/D = L; Complying with both sides arrangement dot inverting.
This pin shuts off the output at the falling edge and then outputs analog display
signals at the rising. When HS = L, after the driver output pin goes to high impedance
this pin switches PL/NL and resets the internal hold capacity and output buffer to the
V
This pin shuts off the output buffer low current supply and increases the output
impedance. The LPC = “H” mode allows the static current consumption to be
reduced by approximately 20 %.
These pins control the current consumption of the output buffer by applying a
stabilized external power supply.
3.3 V 0.3 V
13.5 V
13.5 V
This pin applies the intermediate voltage of a stable LCD drive voltage from a voltage
follower, etc.
Logic ground
High voltage block (level shifter)
High voltage block (output buffer)
High voltage block (sample & hold)
“L” or left open
COM
level.
P-P
MAX.
MAX.
negative analog display signals and outputs positive analog signals from the
driver output.
When PL/NL = L, Both odd number pin and even number pin samples
positive analog display signals and outputs negative analog signals from the
driver output.
and outputs positive analog signals from the driver output. Even number pin
samples positive analog display signals and outputs negative analog signals
from the driver output.
When PL/NL = L, Odd number pin samples positive analog display signals
and outputs negative analog signals from the driver output. Even number pin
samples negative analog display signals and outputs positive analog signals
from the driver output.
analog voltage whose input/output characteristic is gain 1 is output.
;
;
;
SPR input, S
SPL input, S
start pulse input pin
start pulse output pin
start pulse output pin
start pulse input pin
312
1
Description
S
S
312
1
, SPR output
, SPL output
COM
level are performed
DD2
PD16602
12.5 V, a
5