UPD16602N NEC, UPD16602N Datasheet - Page 9

• Manufacturer Part Number: UPD16602N
• Description: 312-OUTPUT TFT-LCD FULL COLOR DRIVER
• Manufacturer: NEC

(4) Relatonship with HS and PL/NL
Caution HS and PL/NL edges have no relationship with clock timing.
These characteristics are specified by load constants of 50 k
(5) Internal sampling delay
t
d1
Horizontal synchronization
setup time
Horizontal synchronization
hold time
Sampling start time
CLK-sampling pulse delay
Sampling pulse-CLK delay
is 22 ±5 ns and t
D
D
D
G0
R0
B0
PL/NL
Timing Duration
(SPL)
SPR
CLK
Timing Item
to D
to D
to D
HS
G3
R3
B3
(input)
(input)
(input)
CLK
SP
SP
t
HS-SETUP
1
2
d2
is 14 ±5 ns (these are not guaranteed values).
Hi-Z
t
Symbol
t
Symbol
HS-SETUP
HS-HOLD
t
HS-SP
t
t
d1
d2
t
HS-HOLD
Setup time of PL/NL signal with respect to HS.
Secure 50 ns
PL/NL hold time. Secure 250 ns
The hold capacitance at this time is at common potential V
buffer does not reach V
Time for the output buffer to reach V
Secure 1.0 s
Input the start pulse at this time.
Delay time between CLK signal and rising edge of internal sampling pulse
SPn.
Input an analog image signal with a timing difference of t
a sufficient sampling period.
Delay time between CLK signal and falling edge of internal sampling pulse.
0 1 2
t
t
HS-SP
d1
Output period
MIN.
Sampling period
MIN
at least.
at least. Sampling is possible at this time.
COM
+ 100 pF.
, and therefore sampling is not possible.
t
d1
MIN.
Description
Description
at least.
COM
26 27
t
d2
(reset level).
0 1 2
d1
COM
in order to secure
, but the output
t
d2
PD16602
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