CY28341 Cypress Semiconductor, CY28341 Datasheet - Page 10

• Manufacturer Part Number: CY28341
• Description: Universal Single-Chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07367 Rev. *A
Maximum Ratings
Input Voltage Relative to V
Input Voltage Relative to V
Storage Temperature: ................................–65 C to + 150 C
Operating Temperature: .................................... 0 C to +70 C
Maximum ESD .............................................................2000V
Maximum Power Supply: ................................................5.5V
DC Parameters
AC Parameters
XTAL
TDC
TPeriod
VHIGH
VLOW
Tr/Tf
TCCJ
Txs
P4 Mode CPU at 0.7V
TDC
TPeriod
Tr/Tf
Delta Tr/Tf Rise/Fall Time Variation
TSKEW
TCCJ
Notes:
Parameter
3.
4.
Parameter
Idd3.3V
Idd2.5V
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
All notes for this table may be found at the end of the table, on page 12.
Ipdwn
Cxtal
VIH1
VIH2
VIL1
VIL2
Cout
Ipup
Lpin
Cin
Vol
Ipd
Ioz
Iol
X
X
X
X
X
X
Crystal Start-up Time
CPUT/C Duty Cycle
CPUT/C Period
CPUT/C Rise and Fall Times
Rise/Fall Matching
CPUCS_T/C to CPUT/C Clock
Skew
CPUT/C Cycle to Cycle Jitter
IN
IN
IN
IN
IN
IN
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage for SRESET#
Pull-down Current for SRESET#
Three-state Leakage Current
Dynamic Supply Current
Dynamic Supply Current
Power-down Supply Current
Internal Pull-up Device Current
Internal Pull-down Device Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Crystal Pin Capacitance
Duty Cycle
Period
High Voltage
Low Voltage
Rise and Fall Times
Cycle to Cycle Jitter
V
DD
Description
[3]
= V
SS
DDQ
DDPCI
:.............................. V
Description
or AV
= V
DD
DDAGP
: ............. V
= V
0.7V
69.841
DDR
–150
Min.
9.85
175
45
45
0
0
DD
SS
DD
= V
100 MHz
+ 0.3V
– 0.3V
DD48M
Measured from the X
CPU Frequency Set at 133.3 MHz
CPU Frequency Set at 133.3 MHz
0.3V
Applicable to SDATA and SCLK
Max.
+150
10.0
20%
71.0
V
10.2
500
700
125
200
55
30
55
Applicable to PD#, F S(0:4)
DD
= V
DD
This device contains circuitry to protect inputs against damage
due to high-static voltages or electric field. However, precau-
tions should be take to avoid application of any voltage higher
than the maximum-rated voltages to this circuit. For proper
operation, V
V
Unused inputs must always be tied to an appropriate logic
voltage level (either V
DDC
SS
Input @ V
Input @ V
Conditions
V
0.7V
= 3.3V ± 5%, V
69.84
< (V
–150
OL
PD# = 0
Min.
7.35
175
45
45
0
0
I
133MHz
= 0.4V
OL
DD
IN
IN
or V
IN
SS
DD
or X
0.3V
+150
and V
Max
71.0
7.65
20%
V
500
700
125
150
OUT
55
10
30
55
DD
OUT
DD
) < V
DDI
OUT
to V
SS
= V
0.7V
DD
69.84
–200
Min.
4.85
or V
should be constrained to the range:
175
[5]
[5]
SS
45
45
0
0
.
DD
200 MHz
DD
DD
= 2.5V ± 5%, T
Min.
2.0
2.2
0.4
24
27
).
0.3V
+200
Max
71.0
20%
V
500
700
125
200
5.1
55
10
30
55
DD
DD
Typ.
150
175
35
95
36
Unit
ms
ns
ns
ps
ns
ps
ps
ps
ps
%
%
V
V
A
CY28341
Max.
= 0°C to +70°C
190
195
600
–25
Page 10 of 21
0.8
1.0
10
10
45
5
6
7
11,15,21,22
11,15,21,22
7,11,14,21,
7,11,14,21,
23,26,24
11,23,22
Notes
23,24
11,12
12,9
7,8
7,8
10
10
22
22
9
Unit
Vdc
Vdc
Vdc
Vdc
mA
mA
mA
pF
pF
pF
pF
V
A
A
A
A
[4]