CY28341 Cypress Semiconductor, CY28341 Datasheet - Page 12

• Manufacturer Part Number: CY28341
• Description: Universal Single-Chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07367 Rev. *A
AC Parameters
Tr / Tf
TCCJ
24MHz
TDC
TPeriod
Tr / Tf
TCCJ
REF
TDC
TPeriod
Tr / Tf
TCCJ
DDR
VX
VD
TDC
TPeriod
Tr / Tf
TSKEW
TCCJ
THPJ
TDelay
TSKEW
tstable
Notes:
10. Measured between 0.2V
12. When X
13. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and
14. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V, and 50% point for differential signals.
15. This measurement is applicable with Spread ON or spread OFF.
16. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals)
17. Probes are placed on the pins, and measurements are acquired at 0.4V.
18. The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within
19. The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same.
20. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary
21. Measured at VX, or where subtraction of CLK-CLK# crosses 0 volts.
22. See Figure 10. for 0.7V loading specification.
23. Measured from Vol=0.175V to Voh=0.525V.
24. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as “the instantaneous
25. Measurement taken from differential waveform, from -0.35V to +0.35V.
26. Measured in absolute voltage, i.e. single-ended measurement.
27. Measured at VX between the rising edge and the following falling edge of the signal.
28. Measured at VX between the falling edge and the following rising edge of the signal.
29. This parameter is intended to be 0.45*Tperiod(min) for minimum spec. and 0.55*Tperiod(min) for maximum spec.
30. Determined as a fraction of 2*(Trise-Tfall)/(Trise+Tfall).
11. All outputs loaded as per loading specified in the Table 11.
Parameter
5.
6.
7.
8.
9.
All outputs loaded as per maximum capacitive load table.
All outputs are not loaded.
This parameter is measured as an average over a 1- s duration, with a crystal center frequency of 14.31818 MHz.
This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
When crystal meets minimum 40-ohm device series resistance specification.
between 20% and 80% for differential signals.
the specifications.
DDRC (and CPUCS_C) one.
difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is
designed for waveform symmetry.
IN
is driven from an external clock source (3.3V parameters apply).
48MHz Rise and Fall Times
48MHz Cycle to Cycle Jitter
24MHz Duty Cycle
24MHz Period
24MHz Rise and Fall Times
24MHz Cycle to Cycle Jitter
REF Duty Cycle
REF Period
REF Rise and Fall Times
REF Cycle to Cycle Jitter
Crossing Point Voltage of
DDRT/C
Differential Voltage Swing
DDRT/C(0:5) Duty Cycle
DDRT/C(0:5) Period
DDRT/C(0:5) Rise/Fall Slew Rate
DDRT/C to Any DDRT/C Clock
Skew
DDRT/C(0:5) Cycle to Cycle Jitter
DDRT/C(0:5) Half-period Jitter
BUF_IN to Any DDRT/C Delay
FBOUT to Any DDRT/CSkew
All Clock Stabilization from
Power-up
(continued)
Description
DD
and 0.7V
DD
.
69.8413
0.5*V
41.660
– 0.2
Min.
9.85
1.0
1.0
1.0
0.7
45
45
45
1
1
100 MHz
DD
0.5*V
V
DDD
41.667
Max.
1000
±100
71.0
10.2
±75
500
500
100
100
4.0
4.0
4.0
0.2
55
55
55
3
4
3
DDD
+ 0.6
+
0.5*V
69.8413
41.660
14.85
– 0.2
Min.
1.0
1.0
1.0
0.7
45
45
45
1
1
133MHz
DDD
0.5*V
V
41.667
1000
+ 0.2
±100
Max
71.0
DDD
15.3
500
500
100
±75
100
4.0
4.0
4.0
0.6
55
55
55
3
4
3
DDD
+
0.5*V
69.8413
41.660
Min.
–0.2
9.85
1.0
1.0
1.0
0.7
45
45
45
1
1
200 MHz
DDD
0.5*V
V
41.667
1000
±100
Max
71.0
+0.2
DDD
10.2
500
500
100
±75
100
4.0
4.0
4.0
0.6
55
55
55
3
4
3
DDD
+
Unit
V/ns
ms
ns
ps
ns
ns
ps
ns
ns
ps
ns
ps
ps
ps
ns
ps
%
%
%
V
V
CY28341
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Notes
7,11,14
7,11,14
7,11,14
7,11,14
11,13
11,13
11,13
11,14
11,14
19
20
21
21
13
18
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