CY28341 Cypress Semiconductor, CY28341 Datasheet - Page 14

• Manufacturer Part Number: CY28341
• Description: Universal Single-Chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07367 Rev. *A
Rise and Fall Times
Power-down Deassertion (P4 Mode)
The power-up latency needs to be less than 3 mS.
AMD K7 Processor SELP4_K7# = 0
Power-down Assertion (K7 Mode)
When the PD# signal is asserted LOW, all clocks are disabled
to a LOW level in an orderly fashion prior to removing power
from the part. When PD# is asserted (forced) LOW, the device
transitions to a shutdown (power-down) mode and all power
supplies may then be removed. When PD# is sampled LOW
S D R A M 1 3 3 M H z
R E F 1 4 .3 1 8 M H z
D D R C 1 3 3 M H z
D D R T 1 3 3 M H z
C P U # 1 3 3 M H z
C P U 1 3 3 M H z
A G P 6 6 M H z
U S B 4 8 M H z
P W R D W N #
P C I 3 3 M H z
Figure 3. Power-down Deassertion Timing Waveform (in P4 Mode)
< 1 .5 m s e c
by two consecutive rising edges of CPU clock, then all affected
clocks are stopped in a LOW state as soon as possible. When
in power-down (and before power is removed), all outputs are
synchronously stopped in a LOW state (see figure3 below), all
PLL’s are shut off, and the crystal oscillator is disabled. When
the device is shutdown, the I2C function is also disabled.
CY28341
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