CY28341 Cypress Semiconductor, CY28341 Datasheet - Page 13

• Manufacturer Part Number: CY28341
• Description: Universal Single-Chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07367 Rev. *A
P4 Processor SELP4_K7# = 1
Power-down Assertion (P4 Mode)
When PD# is sampled LOW by two consecutive rising edges
of CPU# clock then all clock outputs except CPU clocks must
be held LOW on their next HIGH to LOW transition. CPU
clocks must be held with the CPU clock pin driven HIGH with
a value of 2 x Iref, and CPU# undriven. Note that Figure 4
S D R A M 1 3 3 M H z
R E F 1 4 .3 1 8 M H z
C P U T # 1 3 3 M H z
D D R C 1 3 3 M H z
D D R T 1 3 3 M H z
C P U T 1 3 3 M H z
A G P 6 6 M H z
U S B 4 8 M H z
P W R D W N #
P C I 3 3 M H z
Figure 2. Power-down Assertion Timing Waveform (in P4 Mode)
shows CPU = 133 MHz, this diagram and description is appli-
cable for all valid CPU frequencies 66, 100, 133, 200MHz.Due
to the state of internal logic, stopping and holding the REF
clock outputs in the LOW state may require more than one
clock cycle to complete.
CY28341
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