CY28341 Cypress Semiconductor, CY28341 Datasheet - Page 16

• Manufacturer Part Number: CY28341
• Description: Universal Single-Chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07367 Rev. *A
Power-down Deassertion (K7 Mode)
When de-asserted PD# to HIGH level, all clocks are enabled
and start running on the rising edge of the next full period in
Note:
31. This time diagram shows that VTT_PWRGD# transits to a logic LOW in the first time at power-up. After the first HIGH to LOW transition of VTT_PWRGD#,
VDD Clock Gen
VTT_PW RGD#
device is not affected, VTT_PWRGD# is ignored.
Clock Outputs
S D R A M 1 3 3 M H z
Clock State
R E F 1 4 .3 1 8 M H z
Clock VCO
D D R C 1 3 3 M H z
D D R T 1 3 3 M H z
VID (0:3),
C P U # 1 3 3 M H z
SEL (0,1)
PW RGD
C P U 1 3 3 M H z
A G P 6 6 M H z
U S B 4 8 M H z
P W R D W N #
P C I 3 3 M H z
Figure 6. VTT_PWGD# Timing Diagram (With Advanced PIII Processor SelP4_K7 = 1)
State 0
Off
Off
Figure 5. Power-down Deassertion Timing Waveform (in K7 mode)
0.2-0.3m S
State 1
Delay
< 1 .5 m se c
VTT_GD#
W ait for
On
order to guarantee a glitch-free operation, no partial clock
pulses.
Sam ple Sels
State 2
On
State 3
(Note A)
[31]
CY28341
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