IDT72V3612L12PFG IDT, Integrated Device Technology Inc, IDT72V3612L12PFG Datasheet
IDT72V3612L12PFG
Specifications of IDT72V3612L12PFG
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IDT72V3612L12PFG Summary of contents
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FEATURES: • • • • • Two independent clocked FIFOs ( storage capacity each) buffering data in opposite directions • Supports clock frequencies MHz • • • • • Fast access times of 8ns • ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO directional clocked FIFO memory. It supports clock frequencies MHz and has read access times as fast as 8ns. The FIFO operates in IDT Standard mode. Two independent ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO PIN CONFIGURATIONS (CONTINUED GND ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO PIN DESCRIPTION Symbol Name I/O A0-A35 Port A Data I/O AEA Port A Almost-Empty O Flag (Port A) the FIFO2 is less than or equal to the value in the ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO PIN DESCRIPTION (CONTINUED) Symbol Name I/O MBF2 Mail2 Register Flag O ODD/ Odd/Even Parity I EVEN Select PEFA Port A Parity Error O Flag (Port A) PEFB Port B Parity ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC (2) V Input Voltage Range I (2) V Output Voltage Range O I ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3612 with CLKA ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE Commercial: Vcc=3.3V ± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; T Symbol Parameter f Clock Frequency, CLKA ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C Commercial: Vcc=3.3V ± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; T Symbol Parameter t Access Time, CLKA↑ ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO SIGNAL DESCRIPTIONS RESET The IDT72V3612 is reset by taking the Reset (RST) input LOW for at least four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH transitions. ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO and read operations and are not related to high-impedance control of the data outputs port enable is LOW during a clock cycle, the port chip select and write/read ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO more words in memory and is HIGH when the FIFO contains [64-(X+1)] or less words. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO CLKA CLKB t RSTS RST FS1,FS0 FFA EFA FFB EFB AEA AFA t RSF MBF1, MBF2 AEB AFB Figure 2. Device Reset and Loading the X Register with the Value ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO CLK t CLKH t CLKL CLKA FFA HIGH t ENS1 CSA t ENS1 W/RA t ENS3 MBA t ENS2 ENA A35 ODD/ EVEN PEFA NOTE: ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO CLK t t CLKH CLKL CLKB EFB HIGH CSB W/RB t ENS2 MBB ENB t MDV t EN Previous Data B0 - B35 t PGB, ODD/ EVEN NOTE: 1. ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO CLKA CSA LOW W/RA HIGH t t ENH3 ENS3 MBA t t ENS2 ENH2 ENA FFA HIGH A35 t SKEW1 CLKB EFB FIFO1 ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO CLKB CSB LOW W/RB HIGH t t ENS3 ENH3 MBB t t ENS2 ENH2 ENB FFB HIGH B35 t SKEW1 CLKA EFA FIFO2 ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO CLK t t CLKH CLKL CLKB CSB LOW LOW W/RB LOW MBB t ENS2 ENB EFB HIGH B0 - B35 Previous Word in FIFO1 Output Register CLKA FIFO1 Full ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO CLK t t CLKH CLKL CLKA CSA LOW W/RA LOW MBA LOW t ENS2 ENA EFA HIGH A0 - A35 Previous Word in FIFO2 Output Register CLKB FFB FIFO2 ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO CLKB t t ENS2 ENB t SKEW2 CLKA AEA ENA NOTES: is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO CLKA t ENS1 CSA t ENS1 W/RA t ENS1 MBA t ENS1 ENA A0 - A35 CLKB MBF1 CSB W/RB MBB ENB t EN FIFO1 Output Register B0 - B35 ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO CLKB CSB W/RB MBB ENB B0 - B35 CLKA MBF2 CSA W/RA MBA ENA t EN FIFO2 Output Register A0 - A35 NOTE: 1. Port A parity generation off (PGA ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO ODD/ EVEN W/RB MBB PGB t POPE PEFB Valid NOTE: 1. ENB is HIGH, and CSB is LOW. Figure 18. ODD/ EVEN ODD/ EVEN LOW CSA W/RA MBA PGA t ...
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TM IDT72V3612 3.3V, CMOS SyncBiFIFO PARAMETER MEASUREMENT INFORMATION From Output 1.5 V Timing Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 PZL t ...
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ORDERING INFORMATION XXXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range is available by special order. 2. Green parts are available. For specific speeds and packages contact your sales office. DATASHEET DOCUMENT HISTORY 07/10/2000 pg. 1. 05/27/2003 ...