IDT72V3612L12PFG IDT, Integrated Device Technology Inc, IDT72V3612L12PFG Datasheet - Page 9

• Manufacturer Part Number: IDT72V3612L12PFG
• Description: IC FIFO 64X36X2 12NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3612L12PFG

• Function: Asynchronous
• Memory Size: 4.6K (64 x 36 x2)
• Data Rate: 83MHz
• Access Time: 12ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 72V3612L12PFG

Commercial: Vcc=3.3V
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Only applies when reading data from a mail register.
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C
IDT72V3612 3.3V, CMOS SyncBiFIFO
64 x 36 x 2
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A
PAE
MDV
PDPE
POPE
PEPE
EN
DIS
WFF
REF
PAF
PMF
PMR
POPB
PEPB
RSF
(3)
(3)
Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35
Propagation Delay Time, CLKA↑ to FFA and CLKB↑ to FFB
Propagation Delay Time, CLKA↑ to EFA and CLKB↑ to EFB
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2
HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
Propagation Delay Time, CLKA↑ to B0-B35
to A0-A35
Propagation Delay Time, MBA to A0-A35 valid and MBB to
B0-B35 valid
Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35
valid to PEFB valid
Propagation Delay Time, ODD/EVEN to PEFA and PEFB
Propagation Delay Time, ODD/EVEN to parity bits (A8, A17,
A26, A35) and (B8, B17, B26, B35)
Propagation Delay Time, W/RA, CSA, ENA, MBA or PGA to
PEFA; W/RB, CSB, ENB. MBB, PGB to PEFB
Propagation Delay Time, W/RA, CSA, ENA, MBA or PGA to
parity bits (A8, A17, A26, A35); W/RB, CSB, ENB. MBB or PGB
to parity bits (B8, B17, B26, B35)
Propagation Delay Time, RST to (AEA, AEB) LOW and
(AFA, AFB, MBF1, MBF2) HIGH
Enable Time, CSA and W/RA LOW to A0-A35 active and
CSB LOW and W/RB HIGH to B0-B35 active
Disable Time, CSA or W/RA HIGH to A0-A35 at high-
impedance and CSB HIGH or W/RB LOW to B0-B35 at
high impedance
± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; T
(2)
Parameter
TM
(1)
and CLKB↑
9
A
= 0
IDT72V3612L12
°
Min.
C to +70
1
1
1
1
1
1
2
1
2
2
2
1
2
1
2
1
°
C; JEDEC JESD8-A compliant
Max.
10
8
8
8
8
8
8
8
8
8
8
8
8
8
6
6
IDT72V3612L15
Min.
2
2
2
2
2
1
2
1
2
2
2
1
2
1
2
1
COMMERCIAL TEMPERATURE RANGE
Max.
10
10
10
10
10
10
10
10
10
10
10
10
15
10
9
8
IDT72V3612L20
Min.
2
2
2
2
2
1
2
1
2
2
2
1
2
1
2
1
FEBRUARY 12, 2009
L
Max.
11.5
= 30pF
12
12
12
12
12
12
12
11
12
12
12
12
20
12
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns