IDT72V3612L12PFG IDT, Integrated Device Technology Inc, IDT72V3612L12PFG Datasheet - Page 5

• Manufacturer Part Number: IDT72V3612L12PFG
• Description: IC FIFO 64X36X2 12NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3612L12PFG

• Function: Asynchronous
• Memory Size: 4.6K (64 x 36 x2)
• Data Rate: 83MHz
• Access Time: 12ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 72V3612L12PFG

PIN DESCRIPTION (CONTINUED)
IDT72V3612 3.3V, CMOS SyncBiFIFO
64 x 36 x 2
Symbol
MBF2
EVEN
PEFA
PEFB
W/RA
W/RB
ODD/
PGA
PGB
RST
Mail2 Register Flag
Odd/Even Parity
Select
Port A Parity Error
Flag
Port B Parity Error
Flag
Port A Parity
Generation
Port B Parity
Generation
Reset
Port A Write/Read
Select
Port B Write/Read
Select
Name
(Port A)
(Port B)
O
O
O
I/O
I
I
I
I
I
I
TM
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-
HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH
when the device is reset.
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as
A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the
parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The
parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by
having W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the
A0-A35 inputs.
When any byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as
B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity
bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having
W/RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of
the B0-B35 inputs.
Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is
selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26,
and A27-A35. The generated parity bits are output in the most significant bit of each byte.
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is
selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26,
and B27-B35. The generated parity bits are output in the most significant bit of each byte.
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of
CLKB must occur while RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and
the EFA, EFB, AEA, AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches
the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offset.
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-
HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is
HIGH.
A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-
HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is
HIGH.
5
Description
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 12, 2009