IDT72255LA20TF IDT, Integrated Device Technology Inc, IDT72255LA20TF Datasheet - Page 24

• Manufacturer Part Number: IDT72255LA20TF
• Description: IC FIFO 8KX18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72255LA20TF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Access Time: 20ns
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 12ns
• Word Size: 18b
• Organization: 8Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: STQFP
• Clock Freq (max): 50MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 80mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72255LA20TF

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
control signals of multiple devices. Status flags can be detected from
any one device. The exceptions are the EF and FF functions in IDT
Standard mode and the IR and OR functions in FWFT mode. Because
of variations in skew between RCLK and WCLK, it is possible for EF/FF
deassertion and IR/OR assertion to vary by one cycle between FIFOs. In
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
Word width may be increased simply by connecting together the
GATE
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
MASTER RESET (
PARTIAL RESET (
FULL FLAG/INPUT READY (
FULL FLAG/INPUT READY (
RETRANSMIT (
m + n
PROGRAMMABLE (
WRITE CLOCK (WCLK)
WRITE ENABLE (
HALF-FULL FLAG (
Figure 19. Block Diagram of 8,192 x 36 and 16,384 x 36 Width Expansion
)
)
)
D
0
- Dm
LOAD (
/ )
/ ) #2
m
#1
)
)
)
)
72255LA
72265LA
IDT
FIFO
#1
Dm
m
+1
- Dn
Q
24
0
n
- Qm
IDT Standard mode, such problems can be avoided by creating compos-
ite flags, that is, ANDing EF of every FIFO, and separately ANDing FF of
every FIFO. In FWFT mode, composite flags can be created by ORing
OR of every FIFO, and separately ORing IR of every FIFO.
72265LA devices. D0 - D17 from each device form a 36-bit wide input
bus and Q0-Q17 from each device form a 36-bit wide output bus. Any
word width can be attained by adding additional IDT72255LA/72265LA
devices.
Figure 23 demonstrates a width expansion using two IDT72255LA/
72255LA
72265LA
FIFO
IDT
#2
READ CLOCK (RCLK)
n
READ ENABLE (
OUTPUT ENABLE (
EMPTY FLAG/OUTPUT READY (
EMPTY FLAG/OUTPUT READY (
PROGRAMMABLE (
Qm
+1
- Qn
)
COMMERCIAL AND INDUSTRIAL
)
m + n
)
TEMPERATURE RANGES
DATA OUT
/
/
JANUARY 13, 2009
) #2
) #1
4670 drw 22
GATE
(1)