IDT72255LA20TF IDT, Integrated Device Technology Inc, IDT72255LA20TF Datasheet - Page 27

• Manufacturer Part Number: IDT72255LA20TF
• Description: IC FIFO 8KX18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72255LA20TF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Access Time: 20ns
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 12ns
• Word Size: 18b
• Organization: 8Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: STQFP
• Clock Freq (max): 50MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 80mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72255LA20TF

for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.
NOTES:
1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.
2. This is t
3. Tf is the period of the ‘selected clock’.
4. T
5. Typical I
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc and the SuperSyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RCLK
IDT has improved the performance of the IDT72255/72265 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part is pin-
DIFFERENCES BETWEEN THE IDT72255LA/72265LA AND IDT72255L/72265L
is the cycle period of the read clock.
SKEW3
CC1
(FWFT Mode)
Pin #3
First Word Latency
(IDT Standard Mode)
First Word Latency
(FWFT Mode)
Retransmit Latency
(IDT Standard Mode)
Retransmit Latency
I
I
Typical I
CC1
CC2
is based on V
.
Item
CC1
(5)
CC
= 5V, t
A
= 25°C, f
DC (Don’t Care) - There is
no restriction on WCLK and
RCLK. See note 1.
60ns
60ns
60ns
60ns
80mA
20mA
15 + 2.1*f
5 VOLT CMOS SuperSync FIFO
8,192 x 18
16,384 x 18
(2)
(2)
(2)
(2)
S
+ t
+ t
+ t
+ t
= WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at f
IDT72255LA
IDT72265LA
NEW PART
S
REF
REF
REF
REF
+ 0.02*C
+ 1 T
+ 2 T
+ 1 T
+ 2 T
RCLK
RCLK
RCLK
RCLK
L
*f
S
(mA)
(4)
(4)
(4)
(4)
FS (Frequency Select)
t
t
t
t
15mA
Not Given
180mA
FWL1
FWL2
RTF1
RTF2
27
= 14*Tf
= 14*Tf
ADDENDUM
= 10*Tf
= 10*Tf
IDT72255L
IDT72265L
OLD PART
(3)
(3)
(3)
(3)
+ 2T
+ 3T
+ 3T
+ 4T
™
RCLK
RCLK
RCLK
RCLK
(4)
(4)
(4)
(4)
(ns)
(ns)
(ns)
(ns)
In the LA part this pin must be tied
to either V
not toggle after reset.
First word latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
First word latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
Retransmit latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
Retransmit latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
Active supply current
Standby current
Typical I
CC1
Comments
CC
S
Current calculation
/2, C
or GND and must
L
= Capacitive Load (in pF).
IDT72255LA
IDT72265LA