AD8065 AD8066 Analog Devices, AD8065 AD8066 Datasheet - Page 4

• Manufacturer Part Number: AD8065 AD8066
• Description: High Performance, 145 MHz Fast FET Op Amps
• Manufacturer: Analog Devices

AD8065/AD8066–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
NOISE/HARMONIC PERFORMANCE
DC PERFORMANCE
INPUT CHARACTERISTICS
OUTPUT CHARACTERISTICS
POWER SUPPLY
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . See Figure 2
Common-Mode Input Voltage . . V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 1.8 V
Storage Temperature . . . . . . . . . . . . . . . . . . –65∞C to +125∞C
Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Input Overdrive Recovery Time
Output Recovery Time
Slew Rate
Settling Time to 0.1%
SFDR
Third Order Intercept
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
FET Input Range
Usable Range
EE
– 0.5 V to V
Conditions
G = +1, V
G = +1, V
G = +2, V
G = +2, V
G = +2, V
G = +1, –0.5 V to +5.5 V
G = –1, –0.5 V to +5.5 V
G = +2, V
G = +2, V
f
f
f
f = 10 kHz
f = 10 kHz
NTSC, G = +2, R
NTSC, G = +2, R
V
SOIC Package
T
T
V
V
See Theory of Operation section
V
V
R
R
V
SFDR
30% Overshoot G = +1
± PSRR
C
C
C
CM
O
O
CM
CM
L
L
O
MIN
MIN
= 1 MHz, G = +2, V
= 5 MHz, G = +2, V
= 10 MHz, R
= 1 kW
= 150 W
= 1 V to 4 V (AD8065)
= 1 V to 4 V (AD8066)
= 4 V p-p,
CC
= 1 V to 4 V
= 1 V to 2 V (SOT-23)
= 1.0 V, SOIC Package
(@ T
to T
to T
≥ –60 dBc, f = 500 kHz
+ 0.5 V
A
O
O
MAX
MAX
O
O
O
O
O
= 25 C, V
= 0.2 V p-p (AD8065) 125
= 0.2 V p-p (AD8066) 110
= 2 V p-p
= 2 V Step
= 2 V Step
= 0.2 V p-p
= 0.2 V p-p
–4–
L
= 100W
L
L
S
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8065/AD8066
packages is limited by the associated rise in junction temperature
(T
reach the junction temperature. At approximately 150∞C, which
is the glass transition temperature, the plastic will change its
properties. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8065/AD8066.
Exceeding a junction temperature of 175∞C for an extended
period of time can result in changes in the silicon devices,
potentially causing failure.
= 150 W
= 150 W
= 5 V, R
O
O
J
) on the die. The plastic encapsulating the die will locally
= 2 V p-p
= 2 V p-p
L
= 1 k
Min
105
100
90
0 to 1.7
0.1 to 4.85
5
5.8
74
78
78
to 1.5 V, unless otherwise noted.)
Typ
155
130
50
43
6
175
170
160
60
22
7
0.6
0.13
0.16
0.4
1
1
25
1
1
113
103
1000 2.1
1000 4.5
0 to 2.4
0 to 5.0
0.03 to 4.95
0.07 to 4.83
35
75
6.4
5
65
50
100
91
100
Max
1.5
17
5
5
24
7.0
Unit
MHz
MHz
MHz
MHz
MHz
ns
ns
V/ms
ns
dBc
dBc
dBm
nV/÷Hz
fA/÷Hz
%
Degree
mV
mV/
pA
pA
pA
pA
dB
dB
GW pF
GW pF
V
V
dB
dB
V
V
mA
mA
pF
V
mA
dB
REV. B
o
C