IDT72825LB15BG IDT, Integrated Device Technology Inc, IDT72825LB15BG Datasheet - Page 11

• Manufacturer Part Number: IDT72825LB15BG
• Description: IC FIFO SYNC DL 1024X18 121BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72825LB15BG

• Function: Synchronous
• Memory Size: 18.4K (1K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 121-BGA
• Configuration: Quad
• Density: 36Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 1Kx18x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: BGA
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 121
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72825LB15BG

then a signal at this input can neither increment the write offset register
pointer, nor execute a write.
the LD pin is set LOW and REN is set LOW; then, data can be read on the
LOW-to-HIGH transition of the Read clock (RCLK). The act of reading the
control registers employs a dedicated read offset register pointer. (The read
and write pointers operate independently). Offset register content can be
read out in the IDT Standard mode only. It is inhibited in the FWFT mode.
registers.
FIRST LOAD (FLA/FLB)
Daisy Chain Depth Expansion configuration, FLA/FLB is grounded to
indicate it is the first device loaded and is set to HIGH for all other devices
in the Daisy Chain. (See Operating Configurations for further details.)
WRITE EXPANSION INPUT (WXIA/WXIB)
additional information. WXIA/WXIB is connected to Write Expansion Out
(WXOA/WXOB) of the previous device in the Daisy Chain Depth Expansion
mode.
READ EXPANSION INPUT (RXIA/RXIB)
additional information. RXIA/RXIB is connected to Read Expansion Out
(RXOA/RXOB) of the previous device in the Daisy Chain Depth Expansion
mode.
OUTPUTS:
FULL FLAG/INPUT READY (FFA/IRA, FFB/IRB)
FFB) function is selected. When the FIFO is full, FF will go LOW, inhibiting
further write operations. When FF is HIGH, the FIFO is not full. If no reads
are performed after a reset, FF will go LOW after D writes to the FIFO. D =
256 writes for the IDT72805LB, 512 for the IDT72815LB, 1,024 for the
IDT72825LB, 2,048 for the IDT72835LB and 4,096 for the IDT72845LB.
LOW when memory space is available for writing in data. When there is no
longer any free space left, IR goes HIGH, inhibiting further write operations.
IDT72805, 513 for the IDT72815, 1,025 for the IDT72825, 2,049 for the
IDT72835 and 4,097 for the IDT72845. Note that the additional word in
FWFT mode is due to the capacity of the memory plus output register.
EMPTY FLAG/OUTPUT READY (EFA/ORA, EFB/ORB)
(EFA/EFB) function is selected. When the FIFO is empty, EF will go LOW,
inhibiting further read operations. When EF is HIGH, the FIFO is not empty.
goes LOW at the same time that the first word written to an empty FIFO
appears valid on the outputs. OR stays LOW after the RCLK LOW to HIGH
transition that shifts the last word from the FIFO memory to the outputs. OR
goes HIGH only with a true read (RCLK with REN = LOW). The previous
data stays at the outputs, indicating the last word was read. Further data
reads are inhibited until OR goes LOW again.
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled;
The contents of the offset registers can be read on the output lines when
A read and a write should not be performed simultaneously to the offset
For the single device mode, see Table I for additional information. In the
This is a dual purpose pin. For single device mode, see Table I for
This is a dual purpose pin. For single device mode, see Table I for
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FFA/
FF/IR is synchronous and updated on the rising edge of WCLK.
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
In FWFT mode, the Input Ready (IRA/IRB) function is selected. IR goes
In FWFT mode, the Output Ready (ORA/ORB) function is selected. OR
IR will go HIGH after D writes to the FIFO. D = 257 writes for the
11
PROGRAMMABLE ALMOST-FULL FLAG (PAFA/PAFB)
FIFO reaches the almost-full condition. In IDT Standard mode, if no reads
are performed after Reset (RS), the PAF will go LOW after (256-m) writes for
the IDT72805LB, (512-m) writes for the IDT72815LB, (1,024-m) writes for
the IDT72825LB, (2,048–m) writes for the IDT72835LB and (4,096–m) writes
for the IDT72845LB. The offset “m” is defined in the Full Offset register.
m) writes for the IDT72805LB, (513-m) writes for the IDT72815LB, (1,025-
m) writes for the IDT72825LB, (2,049-m) writes for the IDT72835LB and
(4,097-m) writes for the IDT72845LB. The default values for m are noted in
Table 1 and 2.
LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is
reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If
synchronous PAF configuration is selected (see Table I), the PAF is
updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAEA/PAEB)
condition. In IDT Standard mode, PAE will go LOW when there are n words
or less in the FIFO. In FWFT mode, the PAE will go LOW when there are
n+1 words or less in the FIFO. The offset “n” is defined as the Empty offset.
The default values for n are noted in Table 1 and 2.
LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is
reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK).
If synchronous PAE configuration is selected (see Table I), the PAE is
updated on the rising edge of RCLK.
WRITE EXPANSION OUT/HALF-FULL FLAG
(WXOA/HFA, WXOB/HFB)
mode, when Write Expansion In (WXIA/WXIB) and/or Read Expansion In
(RXIA/RXIB) are grounded, this output acts as an indication of a half-full
memory.
the next write cycle, the Half-Full flag goes LOW and will remain set until the
difference between the write pointer and read pointer is less than or equal
to one half of the total memory of the device. The Half-Full flag (HFA/HFB)
is then reset to HIGH by the LOW-to-HIGH transition of the Read Clock
(RCLK). The HF is asynchronous.
of the previous device. This output acts as a signal to the next device in the
Daisy Chain by providing a pulse when the previous device writes to the last
location of memory.
READ EXPANSION OUT (RXOA/RXOB)
(RXIA/RXIB) is connected to Read Expansion Out (RXOA/RXOB) of the
previous device. This output acts as a signal to the next device in the Daisy
Chain by providing a pulse when the previous device reads from the last
location of memory.
DATA OUTPUTS (Q
The PAE flag will go LOW when the FIFO reads the almost-empty
If asynchronous PAE configuration is selected, the PAE is asserted
This is a dual-purpose output. In the Single Device and Width Expansion
After half of the memory is filled, and at the LOW-to-HIGH transition of
In the Daisy Chain Depth Expansion mode, WXI is connected to WXO
In the Daisy Chain Depth Expansion configuration, Read Expansion In
Q0-Q17 are data outputs for 18-bit wide data.
The Programmable Almost-Full flag (PAFA/PAFB) will go LOW when
In FWFT mode, if no reads are performed, PAF will go LOW after (257-
If asynchronous PAF configuration is selected, the PAF is asserted
EF/OR is synchronous and updated on the rising edge of RCLK.
TM
0
-Q
17
, QB
0
-QB
COMMERCIAL AND INDUSTRIAL
17
)
TEMPERATURE RANGES
JANUARY 13, 2009