IDT72825LB15BG IDT, Integrated Device Technology Inc, IDT72825LB15BG Datasheet - Page 9

• Manufacturer Part Number: IDT72825LB15BG
• Description: IC FIFO SYNC DL 1024X18 121BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72825LB15BG

• Function: Synchronous
• Memory Size: 18.4K (1K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 121-BGA
• Configuration: Quad
• Density: 36Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 1Kx18x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: BGA
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 121
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72825LB15BG

TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET
NOTES:
1. In a daisy-chain depth expansion, FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.
2. In a daisy-chain depth expansion, FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and
TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD MODE
TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
0
1
WXO outputs of the preceding device.
FL
Output Ready (OR)
0
0
0
1
1
1
(1)
(2)
Buffered Output
Empty Flag (EF)
Double
Double
Single
Single
Triple
Triple
RXI
0
0
1
1
0
0
1
1
WXI
0
1
0
1
0
1
0
1
Single register-buffered
Empty Flag
Triple register-buffered
Output Ready Flag
Double register-buffered
Empty Flag
Single register-buffered
Empty Flag
Single register-buffered
Empty Flag
Triple register-buffered
Output Ready Flag
Double register-buffered
Empty Flag
Single register-buffered
Empty Flag
Buffered Output
Input Ready (IR)
Full Flag (FF)
Double
Double
Single
Single
Double
Double
EF/OR
Timing Mode
Partial Flags
Partial Flags
Single register-buffered
Full Flag
Double register-buffered
Input Ready Flag
Double register-buffered
Full Flag
Single register-buffered
Full Flag
Single register-buffered
Full Flag
Double register-buffered
Input Ready Flag
Double register-buffered
Full Flag
Single register-buffered
Full Flag
Asynch
Asynch
Asynch
Synch
Sync
Sync
9
FF/IR
TM
FL
FL
0
0
1
0
1
1
Programming at Reset
Programming at Reset
RXI
RXI
1
1
0
0
0
0
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Asynchronous
PAE, PAF
COMMERCIAL AND INDUSTRIAL
WXI
WXI
0
0
0
0
1
1
TEMPERATURE RANGES
FIFO TIMING MODE
JANUARY 13, 2009
Figure 24, 26
Figure 24, 26
Flag Timing
Flag Timing
Figure 9, 10
Figure 9, 10
Figure 20, 21
Diagrams
Standard
Standard
Standard
Standard
Standard
Standard
Diagrams
Figure 27
FWFT
FWFT