IDT72825LB15BG IDT, Integrated Device Technology Inc, IDT72825LB15BG Datasheet - Page 20

• Manufacturer Part Number: IDT72825LB15BG
• Description: IC FIFO SYNC DL 1024X18 121BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72825LB15BG

• Function: Synchronous
• Memory Size: 18.4K (1K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 121-BGA
• Configuration: Quad
• Density: 36Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 1Kx18x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: BGA
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 121
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72825LB15BG

NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. t
5. PAE is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
WCLK
WCLK
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
RCLK
RCLK
WEN
WEN
REN
REN
PAE
PAF
rising edge of RCLK is less than t
SKEW2
In IDT Standard Mode: D = 256 for the IDT72805, 512 for the IDT72815, 1,024 for the IDT72825, 2,048 for the IDT72835 and 4,096 for the IDT72845.
In FWFT Mode: D = 257 for the IDT72805, 513 for the IDT72815, 1,025 for the IDT72825, 2,049 for the IDT72835 and 4,097 for the IDT72845.
the rising edge of WCLK is less than t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and
D-(m+1) Words in FIFO
t
n words in FIFO
n + 1words in FIFO
t
CLKH
CLKH
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
ENS
t
ENS
t
SKEW2
t
t
CLKL
CLKL
SKEW2
(2)
,
(4)
(3)
SKEW2
, then the PAE deassertion may be delayed one extra RCLK cycle.
, then the PAF deassertion time may be delayed an extra WCLK cycle.
t
PAFS
t
t
ENH
ENH
t
PAES
20
n + 1 words in FIFO
n + 2 words in FIFO
D - m Words in FIFO
TM
t
t
ENS
ENS
(2)
(3)
,
t
SKEW2
t
t
ENH
ENH
(3)
COMMERCIAL AND INDUSTRIAL
t
PAES
t
PAFS
TEMPERATURE RANGES
JANUARY 13, 2009
n Words in FIFO
n + 1 words in FIFO
D -(m+1) Words
in FIFO
3139 drw 22
3139 drw 23
(2)
,
(3)