IDT72V291L10PF IDT, Integrated Device Technology Inc, IDT72V291L10PF Datasheet
IDT72V291L10PF
Specifications of IDT72V291L10PF
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IDT72V291L10PF Summary of contents
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FEATURES: • • • • • Choose among the following memory organizations: IDT72V281 65,536 x 9 IDT72V291 131,072 x 9 • • • • • Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs • • • • • 10ns read/write cycle time ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 DESCRIPTION (Continued) SuperSync FIFOs are particularly appropriate for network, video, telecommu- nications, data communications and other applications that need to buffer large amounts of data. The input port ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 DESCRIPTION (Continued) In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 ELECTRICAL CHARACTERISTICS o (Commercial 3.3V ± 0.3V + Symbol Parameter f Clock Cycle Frequency S t Data Access ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72V281/72V291 support two different timing modes of opera- tion: IDT Standard mode or First ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 addition to loading offset values into the FIFO, it also possible to read the current offset values only possible to read offset values via parallel ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 72V281 (65,536 x 9›BIT EMPTY OFFSET (LSB) REGISTER DEFAULT VALUE 7FH LOW at Master Reset FFH HIGH at Master Reset ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combination of ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 Parallel reading of the offset registers is always permitted regardless of which timing mode (IDT Standard or FWFT modes) has been selected. RETRANSMIT OPERATION The Retransmit operation allows ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 9-bit wide data. CONTROLS: MRS MRS MRS MRS) MASTER RESET (MRS A Master Reset ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 When WEN is HIGH, no new data is written in the RAM array on each WCLK cycle. To prevent data overflow in the IDT Standard mode, FF will ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 PROGRAMMABLE ALMOST-FULL FLAG (PAF The Programmable Almost-Full flag (PAF) will go LOW when the FIFO reaches the almost-full condition. In IDT Standard mode reads are performed ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 RCLK t t ENS ENH t RTS REN WCLK t RTS WEN t ENS RT EF PAE HF PAF ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 RCLK t t ENH ENS t RTS REN WCLK t RTS WEN t ENS RT OR PAE HF PAF NOTES: 1. ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 CLK t t CLKH CLKL WCLK t LDS LD t ENS WEN PAE OFFSET (LSB) Figure 14. Parallel Loading of ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 CLKH CLKL WCLK t t ENS ENH WEN PAF D - (m+1) words in FIFO RCLK REN NOTES PAF offset . 2. D ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 FWFT/SI FWFT/SI WRITE CLOCK WCLK WRITE ENABLE WEN IDT INPUT READY IR 72V281 72V291 n DATA IN Dn Figure 22. Block Diagram of 131,072 x 9 and 262,144 ...
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ORDERING INFORMATION XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. 2. Green parts are available, for specific speeds and packages contact your sales office. ...