IDT72V291L10PF IDT, Integrated Device Technology Inc, IDT72V291L10PF Datasheet - Page 8

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IDT72V291L10PF

Manufacturer Part Number
IDT72V291L10PF
Description
IC FIFO SS 32768X36 10NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V291L10PF

Function
Synchronous
Memory Size
1.1M (32K x 36)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V291L10PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V291L10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V291L10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
current offset values. It is only possible to read offset values via parallel read.
rizes the control pins and sequence for both serial and parallel programming
modes. For a more detailed description, see discussion that follows.
TABLE 1 ⎯ STATUS FLAGS FOR IDT STANDARD MODE
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2 ⎯ STATUS FLAGS FOR FWFT MODE
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
In addition to loading offset values into the FIFO, it also possible to read the
Figure 4, Programmable Flag Offset Programming Sequence, summa-
Number of
Words in
FIFO
Number of
Words in
FIFO
32,770 to (65,537-(m+1))
32,769 to (65,536-(m+1))
(65,536-m)
(65,537-m)
(n+2) to 32,769
(n+1) to 32,768
72V281
1 to n
65,537
65,536
72V281
1 to n+1
0
(2)
0
to 65,536
to 65,535
(1)
TM
(1)
(2)
65,538 to (131,073-(m+1))
(131,073-m)
(131,072-m)
65,537 to (131,072-(m+1))
8
after Master Reset, regardless of whether serial or parallel programming
has been selected.
(n+2) to 65,537
The offset registers may be programmed (and reprogrammed) any time
(n+1) to 65,536
72V291
1 to n+1
72V291
131,073
1 to n
131,072
0
0
(2)
to 131,072
(1)
to 131,071
(1)
(2)
FF
IR
H
H
H
H
H
L
L
L
L
L
H
L
COMMERCIAL AND INDUSTRIAL
PAF HF
PAF HF
H
H
H
H
H
H
H
H
L
L
L
L
TEMPERATURE RANGES
H
H
H
L
L
L
H
H
H
L
L
L
PAE EF
PAE OR
H
H
H
H
L
L
H
H
H
H
L
L
4513 drw 05
H
H
H
H
H
H
L
L
L
L
L
L

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