IDT72V291L10PF IDT, Integrated Device Technology Inc, IDT72V291L10PF Datasheet - Page 2

• Manufacturer Part Number: IDT72V291L10PF
• Description: IC FIFO SS 32768X36 10NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V291L10PF

• Function: Synchronous
• Memory Size: 1.1M (32K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V291L10PF

SuperSync FIFOs are particularly appropriate for network, video, telecommu-
nications, data communications and other applications that need to buffer large
amounts of data.
Enable (WEN) input. Data is written into the FIFO on every rising edge of
WCLK when WEN is asserted. The output port is controlled by a Read
Clock (RCLK) input and Read Enable (REN) input. Data is read from the
FIFO on every rising edge of RCLK when REN is asserted. An Output
Enable (OE) input is provided for three-state control of the outputs.
PIN CONFIGURATIONS
NOTES:
1. DC = Don’t Care. Must be tied to GND or V
2. This pin may either be tied to ground or left open.
3. DNC = Do Not Connect.
DESCRIPTION (Continued)
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
The input port is controlled by a Write Clock (WCLK) input and a Write
PIN 1
GND
GND
GND
GND
GND
GND
GND
GND
GND
WEN
SEN
DC
V
V
D8
D7
CC
CC
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
CC
1
, cannot be left open.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TM
STQFP (PP64-1, order code: TF)
TQFP (PN64-1, order code: PF)
TOP VIEW
2
to f
of the one clock input with respect to the other.
IDT Standard mode and First Word Fall Through (FWFT) mode.
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and
enabling a rising RCLK edge, will shift the word from internal memory to the
data output lines.
MAX
The frequencies of both the RCLK and the WCLK signals may vary from 0
In IDT Standard mode, the first word written to an empty FIFO will not
There are two possible timing modes of operation with these devices:
with complete independence. There are no restrictions on the frequency
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMMERCIAL AND INDUSTRIAL
4513 drw 02
TEMPERATURE RANGES
DNC
DNC
GND
DNC
DNC
V
DNC
DNC
DNC
GND
DNC
DNC
Q8
Q7
Q6
GND
CC
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)