MT18LD1672AG-5X Micron, MT18LD1672AG-5X Datasheet - Page 14

• Manufacturer Part Number: MT18LD1672AG-5X
• Description: 16 MEG x 72 NONBUFFERED DRAM DIMM
• Manufacturer: Micron

NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate
10.If CAS# and RAS# = V
11.If CAS# = V
12.Measured with a load equivalent to two TTL gates
13.Requires that
14.Requires that
15.If CAS# is LOW at the falling edge of RAS#, Q will
16.The
17.The
18.Either
8, 16, 32 Meg x 72 Nonbuffered DRAM DIMMs
DM79.p65 – Rev. 2/99
MHz.
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range is ensured.
up, followed by eight RAS# REFRESH cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
refresh requirement is exceeded.
measuring timing of input signals. Transition
times are measured between V
between V
specification, all input signals must transit
between V
monotonic manner.
the last valid READ cycle.
and 100pF and V
be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for
t
only. If
(MAX) limit, then access time was controlled
exclusively by
applied). With or without the
t
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
or without the
t
cycle.
RCD (MAX) was specified as a reference point
AA and
RAD was greater than the specified
CAC must always be met.
CC
IH
t
is dependent on output loading and cycle
AA (
(MIN) and V
t
t
RCD (MAX) limit is no longer specified.
RAD (MAX) limit is no longer specified.
t
RCH or
t
t
RCD was greater than the specified
t
RAC and
CAC must always be met.
IL
IH
IL
and V
and V
, data output may contain data from
t
t
AA and
AA and
t
t
t
CAC (
RAD (MAX) limit,
RRH must be satisfied for a READ
IL
OL
t
(MAX) are reference levels for
IH
CAC no longer applied). With
IL
= 0.8V and V
).
(or between V
t
IH
RAC [MIN] no longer
t
t
CAC are not violated.
RAC are not violated.
, data output is High-Z.
t
CP.
t
T = 2ns.
SS
DD
.
IH
t
RCD (MAX) limit,
= +3.3V; f = 1
and V
OH
t
IL
AA,
= 2V.
t
RAD (MAX)
and V
IL
t
RAC and
(or
t
IH
REF
t
) in a
RCD
t
RAD
14
19.
20.A HIDDEN REFRESH may also be performed after
21.The maximum current ratings are based with the
22.These parameters are referenced to CAS# leading
23.
24.Column address changed once each cycle.
25.The 3ns minimum parameter guaranteed by
26.Measured with the specified current load and
27.
28.The SPD EEPROM WRITE cycle time (
29.If OE# is tied permanently LOW, LATE WRITE or
30.All other inputs at 0.2V or V
31. V
t
achieves the open circuit condition and is not
referenced to V
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
memory operating or being refreshed in the x72
mode. The stated maximums may be reduced by
approximately one-half when used in the x36
mode.
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
t
operating parameters.
WRITE cycles. If
an EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle.
MODIFY-WRITE cycles. Meeting these limits
allows for reading and disabling output data and
then applying input data. OE# held HIGH and
WE# taken LOW after CAS# goes LOW result in a
LATE WRITE (OE#-controlled) cycle.
t
WRITE cycle.
design.
100pF.
t
latter of the RAS# and CAS# signals to transition
HIGH.
time from a valid stop condition of a write
sequence to the end of the EEPROM internal
erase/program cycle. During the WRITE cycle, the
EEPROM bus interface circuit are disabled, SDA
remains HIGH due to pull-up resistor, and the
EEPROM does not respond to its slave address.
READ-MODIFY-WRITE operations are not
possible.
width
greater than one third of the cycle rate. V
undershoot: V
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
OFF (MAX) defines the time at which the output
WCS,
CWD and
OFF on an EDO module is determined by the
NONBUFFERED DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
overshoot: V
t
t
RWD,
RWD,
10ns, and the pulse width cannot be
t
AWD are not applicable in a LATE
t
t
AWD and
AWD and
IL
OH
t
(MIN) = -2V for a pulse width
WCS >
IH
or V
8, 16, 32 MEG x 72
(MAX) = V
t
OL
WCS applies to EARLY
t
t
t
CWD define READ-
.
WCS (MIN), the cycle is
CWD are not restrictive
DD
DD
- 0.2V.
+ 2V for a pulse
©1999, Micron Technology, Inc.
t
WCS,
t
WR) is the
IL
t
RWD,