MT18LD1672AG-5X Micron, MT18LD1672AG-5X Datasheet - Page 2

• Manufacturer Part Number: MT18LD1672AG-5X
• Description: 16 MEG x 72 NONBUFFERED DRAM DIMM
• Manufacturer: Micron

GENERAL DESCRIPTION
MT36LD3272A X are randomly accessed 64MB, 128MB
and 256MB memories organized in a x72 configura-
tion. They are specially processed to operate from 3V to
3.6V for low-voltage memory systems.
addressed through the 22/23 address bits, which are
entered 12 bits (A0-A11) at RAS# time and 11/12 bits
(A0-A11) at CAS# time.
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs
when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data-outputs (Q) will remain
High-Z regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data-outputs prior to apply-
ing input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping OE# LOW, no WRITE
will occur, and the data-outputs will drive read data
from the accessed location.
EDO PAGE MODE
MODE cycle. The primary advantage of EDO is the
availability of data-out even after CAS# goes back HIGH.
EDO provides for CAS# precharge time (
without the output data going invalid. This elimina-
tion of CAS# output control provides for pipelined
READs.
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO-PAGE-MODE DRAMs operate like
FAST-PAGE-MODE DRAMs, except data will remain
valid or become valid after CAS# goes HIGH during
READs, provided RAS# and OE# are held LOW. If OE# is
pulsed while RAS# and CAS# are LOW, data will toggle
from valid data to High-Z and back to the same valid
8, 16, 32 Meg x 72 Nonbuffered DRAM DIMMs
DM79.p65 – Rev. 2/99
The Micron
During READ or WRITE cycles, each bit is uniquely
READ and WRITE cycles are selected with the WE#
EDO PAGE MODE is an accelerated FAST-PAGE-
FAST-PAGE-MODE modules have traditionally
®
MT9LD872A X, MT18LD1672A X and
t
CP) to occur
2
data. If OE# is toggled or pulsed after CAS# goes HIGH
while RAS# remains LOW, data will transition to and
remain High-Z.
OR’d, OE# must be used to disable idle banks of DRAMs.
Alternatively, pulsing WE# to the idle banks during
CAS# HIGH time will also tristate the outputs. Indepen-
dent of OE# control, the outputs will disable after
which is referenced from the rising edge of RAS# or
CAS#, whichever occurs last. (Refer to the 16 Meg x 4
[MT4LC16M4H9] DRAM data sheet for additional in-
formation on EDO functionality.)
REFRESH
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time. Correct memory
cell data is preserved by maintaining power and execut-
ing any RAS# cycle (READ, WRITE) or RAS# REFRESH
cycle (RAS#-ONLY, CBR or HIDDEN) so that all combi-
nations of RAS# addresses (A0-A10/A11) are executed at
least every
FRESH cycle will invoke the internal refresh counter for
automatic
addressing.
SERIAL PRESENCE-DETECT OPERATION
detect (SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various DRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations be-
tween the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard IIC bus using the
DIMM’s SCL (clock) and SDA (data) signals, together
with SA(2:0), which provide 8 unique DIMM/EEPROM
addresses.
During an application, if the DQ outputs are wire
Returning RAS# and CAS# HIGH terminates a
This module family incorporates serial presence-
NONBUFFERED DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
REF, regardless of sequence. The CBR RE-
8, 16, 32 MEG x 72
©1999, Micron Technology, Inc.
RAS#
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OFF,