D6376 NEC, D6376 Datasheet - Page 5

• Manufacturer Part Number: D6376
• Description: Search -----> UPD6376
• Manufacturer: NEC

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2. INPUT SIGNAL FORMAT
• Input data must be input as 2’s complement, MSB first.
the table below.
• Synchronize the (SI, LSI, RSI) data bit delimitations and the LRCK, WDCK reverse timing to the falling edge of
• CLK requires the input of 16 clocks between sample data (16 bits). Also, make the time interval for 1 bit the same
(MSB)
2’s complement is a method of expressing both positive numbers and negative numbers as binary numbers. See
Note When A.V
CLK.
as 1 clock cycle.
0111
0111
0000
0000
1111
1000
1000
Values differ depending on IC fabrication variations, supply voltage fluctuations, and ambient temperature.
1111
1111
0000
0000
1111
0000
0000
DD
2’s Complement
= 5.0 V
1111
1111
0000
0000
1111
0000
0000
1111
1110
0001
0000
1111
0001
0000
(LSB)
Decimal Number
+32767
+32766
–32767
–32768
+1
–1
0
L.OUT, R.OUT Pin Voltage TYP. (V)
(Reference Values)
2.6
1.6
0.6
PD6376
Note
5
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