D6376 NEC, D6376 Datasheet - Page 6

• Manufacturer Part Number: D6376
• Description: Search -----> UPD6376
• Manufacturer: NEC

www.DataSheet.co.kr
2.1 Supplying Clock to CLK even outside Sample Data Interval
2.1.1 Serial data input (Pin 1 is Low or Open)
2-1).
2.1.2. Inputting parallel data (Pin 1 is High)
data (LSI, RSI) (Point A in Figure 2-2.).
6
LRCK
WDCK
CLK
CLK
Synchronize the reverse timing of LRCK with the falling edge of CLK upon completion of LSB input (Point A in Figure
Synchronize the timing of the falling edge of WDCK with the falling edge of CLK upon completion of LSB input of
RSI
LSI
SI
LSB
LSB
LSB
16
16
16
A
A
MSB
MSB
MSB
1 2
1 2
1 2
Figure 2-1 Timing Chart for Serial Data Input
Figure 2-2 Parallel Data Input Timing Chart
3 4
3 4
3 4
5
5
5
Interval of 1 sample data
6
6
6
7
7
7
8
8
8
9 10 11 12 13 14 15 16
9 10 11 12 13 14 15 16
9 10 11 12 13 14 15 16
LSB
LSB
LSB
A
A
MSB
MSB
MSB
1 2
1 2
1 2
3 4
PD6376
Datasheet pdf - http://www.DataSheet4U.net/