SC16C754B NXP Semiconductors, SC16C754B Datasheet - Page 33

• Manufacturer Part Number: SC16C754B
• Description: 5 V - 3.3 V and 2.5 V quad UART - 5 Mbit/s (max.)
• Manufacturer: NXP Semiconductors

NXP Semiconductors
8. Programmer’s guide
SC16C754B_4
Product data sheet
The FIFO ready register is a read-only register that can be accessed when any of the four
UARTs is selected CSA to CSD = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loopback
is disabled. The address is 111.
The base set of registers that is used during high-speed data transfer have a
straightforward access method. The extended function registers require special access
bits to be decoded along with the address lines. The following guide will help with
programming these registers. Note that the descriptions below are for individual register
access. Some streamlining through interleaving can be obtained when programming all
the registers.
Table 23.
Command
set baud rate to VALUE1, VALUE2
set Xoff1, Xon1 to VALUE1, VALUE2
set Xoff2, Xon2 to VALUE1, VALUE2
set software flow control mode to VALUE
set flow control threshold to VALUE
Register programming guide
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Rev. 04 — 6 October 2008
Actions
read LCR (03h), save in temp
set LCR (03h) to 80h
set DLL (00h) to VALUE1
set DLM (01h) to VALUE2
set LCR (03h) to temp
read LCR (03h), save in temp
set LCR (03h) to BFh
set Xoff1 (06h) to VALUE1
set Xon1 (04h) to VALUE2
set LCR (03h) to temp
read LCR (03h), save in temp
set LCR (03h) to BFh
set Xoff2 (07h) to VALUE1
set Xon2 (05h) to VALUE2
set LCR (03h) to temp
read LCR (03h), save in temp
set LCR (03h) to BFh
set EFR (02h) to VALUE
set LCR (03h) to temp
read LCR (03h), save in temp1
set LCR (03h) to BFh
read EFR (02h), save in temp2
set EFR (02h) to 10h + temp2
set LCR (03h) to 00h
read MCR (04h), save in temp3
set MCR (04h) to 40h + temp3
set TCR (06h) to VALUE
set MCR (04h) to temp3
set LCR (03h) to BFh
set EFR (02h) to temp2
set LCR (03h) to temp1
SC16C754B
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