SC16C754B NXP Semiconductors, SC16C754B Datasheet - Page 6

• Manufacturer Part Number: SC16C754B
• Description: 5 V - 3.3 V and 2.5 V quad UART - 5 Mbit/s (max.)
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 2.
SC16C754B_4
Product data sheet
Symbol
A0
A1
A2
CDA
CDB
CDC
CDD
CLKSEL
Pin
LQFP64 LQFP80 PLCC68
24
23
22
64
18
31
49
-
Pin description
5.2 Pin description
30
29
28
79
23
39
63
26
Fig 4.
34
33
32
9
27
43
61
30
Pin configuration for PLCC68
DSRA
DSRB
DTRA
DTRB
CTSA
RTSA
RTSB
CTSB
INTA
INTB
GND
CSA
CSB
IOW
V
TXA
TXB
CC
Type
I
I
I
I
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Rev. 04 — 6 October 2008
Description
Address 0 select bit. Internal registers address selection.
Address 1 select bit. Internal registers address selection.
Address 2 select bit. Internal registers address selection.
Carrier Detect (active LOW). These inputs are associated with
individual UART channels A through D. A logic LOW on these pins
indicates that a carrier has been detected by the modem for that channel.
The state of these inputs is reflected in the Modem Status Register
(MSR).
Clock Select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable
clock. During the reset, a logic 1 (V
divide-by-1 prescaler. A logic 0 (GND) on CLKSEL selects the divide-by-4
prescaler. The value of CLKSEL is latched into MCR[7] at the trailing
edge of RESET. A logic 1 (V
MCR[7]. A logic 0 (GND) on CLKSEL will latch a logic 1 into MCR[7].
MCR[7] can be changed after RESET to alter the prescaler value. This
pin is associated with LQFP80 and PLCC68 packages only. This pin is
connected to V
CC
SC16C754BIA68
internally on LQFP64 package.
CC
) on CLKSEL will latch a logic 0 into
CC
) on CLKSEL selects the
SC16C754B
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© NXP B.V. 2008. All rights reserved.
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
V
DTRC
CTSC
DSRC
CC
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