SC16C754B NXP Semiconductors, SC16C754B Datasheet - Page 38

• Manufacturer Part Number: SC16C754B
• Description: 5 V - 3.3 V and 2.5 V quad UART - 5 Mbit/s (max.)
• Manufacturer: NXP Semiconductors

NXP Semiconductors
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SC16C754B_4
Product data sheet
Fig 15. General write timing
Fig 16. General read timing
Applies to external clock, crystal oscillator max 24 MHz.
Maximum frequency =
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
RESET pulse must happen when CS, IOW, IOR signals are inactive.
D0 to D7
D0 to D7
A0 to A2
A0 to A2
IOW
CSx
CSx
IOR
11.1 Timing diagrams
-------------- -
t
w clk
1
t
t
6s
6s
t
t
13d
7d
address
address
t
valid
valid
12d
active
active
active
active
t
13w
t
7w
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Rev. 04 — 6 October 2008
t
16s
data
data
t
t
t
16h
12h
t
13h
t
t
6h
6h
7h
t
15d
t
9d
SC16C754B
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© NXP B.V. 2008. All rights reserved.
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