MBM29PL32BM Fujitsu Media Devices, MBM29PL32BM Datasheet - Page 34

• Manufacturer Part Number: MBM29PL32BM
• Description: (MBM29PL32TM/BM) FLASH MEMORY CMOS 32 M (4M X 8/2M X 16) BIT MirrorFlash
• Manufacturer: Fujitsu Media Devices

34
MBM29PL32TM/BM
Reading Toggle Bits DQ
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ
*2 : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ
DQ
Write-to-Buffer Abort
RY/BY
Ready/Busy
Program
Erase
Erase-Suspend-Read
Erase-Suspend-Program
(Erase-Suspended Sector)
Whenever the system initially begins reading Toggle bit status, it must read DQ
to determine whether a Toggle bit is toggling. Typically a system would note and store the value of the Toggle
bit after the first read. After the second read, the system would compare the new value of the Toggle bit with the
first. If the Toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ
However, if, after the initial two read cycles, the system determines that the Toggle bit is still toggling, the system
also should note whether the value of DQ
determine again whether the Toggle bit is toggling, since the Toggle bit may have stopped toggling just as DQ
went high. If the Toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the Toggle bit is toggling and DQ
gone high. The system may continue to monitor the Toggle bit and DQ
mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of the operation. (Refer to “Toggle Bit Algorithm” in FLOW CHART.)
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1".
The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array
data. See "Write Buffer Programming Operations" section for more details.
The device provides a RY/BY open-drain output pin to indicate to the host system that the Embedded Algorithms
are either in progress or has been completed. If the output is low, the device is busy with either a program or
erase operation. If the output is high, the device is ready to accept any read/write or erase operation. If the
device is placed in an Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-
up resister to V
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. See “RY/BY Timing Diagram during Program/Erase Operation Timing
Diagram” and “RESET Timing Diagram ( During Embedded Algorithms )” in SWITCHING WAVEFORM for a
detailed timing diagram. The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
1
Mode
CC
.
6
7
/ DQ
to DQ
2
0
on the following read cycle.
90/10
5
DQ
DQ
DQ
is high (see the section on DQ
Toggle Bit Status
0
1
7
7
7
Toggle
Toggle
Toggle
DQ
1
5
6
through successive read cycles, deter-
2
5
) . If it is, the system should then
to toggle.
7
to DQ
2
bit.
0
at least twice in a row
Toggle *
Toggle *
DQ
1 *
1
2
2
1
1
5
has not
CC
.
5