MBM29PL32BM Fujitsu Media Devices, MBM29PL32BM Datasheet - Page 35

• Manufacturer Part Number: MBM29PL32BM
• Description: (MBM29PL32TM/BM) FLASH MEMORY CMOS 32 M (4M X 8/2M X 16) BIT MirrorFlash
• Manufacturer: Fujitsu Media Devices

Word/Byte Configuration
Data Protection
BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the
device operates in the word (16-bit) mode. Data is read and programmed at DQ
low, the device operates in byte (8-bit) mode. In this mode, DQ
DQ
mands are written at DQ
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power up the device automatically reset the internal
state machine in Read mode. Also, with its control register architecture, alteration of memory contents only
occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
(1) Low V
To avoid initiation of a write cycle during V
than V
Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the V
is greater than V
unintentional writes when V
If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid.
(2) Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
(3) Logical Inhibit
Writing is inhibited by holding any one of OE = V
be a logical zero while OE is a logical one.
(4) Power-up Write Inhibit
Power-up of the devices with WE = CE = V
The internal state machine is automatically reset to read mode on power-up.
(5) Sector Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voids
both write and erase commands that are addressed to protected sectors.
Any commands to write or erase addressed to protected sector are ignored .
14
to DQ
LKO
. If V
CC
8
Write Inhibit
bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence com-
CC
< V
LKO
. It is the user’s responsibility to ensure that the control pins are logically correct to prevent
LKO
, the command register is disabled and all internal program/erase circuits are disabled.
7
to DQ
CC
is above V
0
and DQ
LKO
15
CC
IL
.
to DQ
and OE = V
power-up and power-down, a write cycle is locked out for V
IL
8
, CE = V
bits are ignored.
IH
will not accept commands on the rising edge of WE.
IH
, or WE = V
MBM29PL32TM/BM
15
/A
-1
pin becomes the lowest address bit, and
IH
. To initiate a write, CE and WE must
15
to DQ
0
. When this pin is driven
CC
power-up
CC
CC
90/10
level
less
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