74AC74SJX Fairchild Semiconductor, 74AC74SJX Datasheet

74AC74SJX

Manufacturer Part Number

74AC74SJX

Description

IC FLIP FLOP DUAL D POS 14SOP

Manufacturer

Fairchild Semiconductor

Series

74ACr

Type

D-Typer

Datasheet

1.74AC74SJX.pdf (10 pages)

Specifications of 74AC74SJX

Function

Set(Preset) and Reset

Output Type

Differential

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

165MHz

Delay Time - Propagation

6ns

Trigger Type

Positive Edge

Current - Output High, Low

24mA, 24mA

Voltage - Supply

2 V ~ 6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

14-SOIC (5.3mm Width), 14-SOP, 14-SOIJ

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74AC74SC

74AC74SC_NL

(Note 1)

74AC74SJ

74AC74MTC

74AC74MTCX_NL

(Note 2)

74AC74PC

74ACT74SC

74ACT74SC_NL

(Note 1)

74ACT74SJ

74ACT74SJX_NL

(Note 2)

74ACT74MTC

74ACT74PC

74AC74 • 74ACT74

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description

The AC/ACT74 is a dual D-type flip-flop with Asynchronous

Clear and Set inputs and complementary (Q, Q) outputs.

Information at the input is transferred to the outputs on the

positive edge of the clock pulse. Clock triggering occurs at

a voltage level of the clock pulse and is not directly related

to the transition time of the positive-going pulse. After the

Clock Pulse input threshold voltage has been passed, the

Data input is locked out and information present will not be

transferred to the outputs until the next rising edge of the

Clock Pulse input.

Asynchronous Inputs:

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Pb-Free package per JECED J-STD-020B.

Note 1: “_NL” indicates lead-free product (per JEDEC J-STD-020B).

Note 2: “_NL” indicates lead-free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.

FACT

Order Number

LOW input to S

LOW input to C

Clear and Set are independent of clock

Simultaneous LOW on C

HIGH

is a trademark of Fairchild Semiconductor Corporation.

(Set) sets Q to HIGH level

(Clear) sets Q to LOW level

Package

Number

MTC14

M14D

M14A

N14A

M14A

N14A

and S

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

makes both Q and Q

DS009920

Features

Output source/sink 24 mA

ACT74 has TTL-compatible inputs

Package Description

reduced by 50%

November 1988

Revised February 2005

www.fairchildsemi.com

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