upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 489

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

A/D
converter
Serial
interface
UART0
Function
Input
impedance of
ANI0 to ANI7
pins
AV
impedance
Interrupt
request flag
(ADIF)
Conversion
results just after
A/D conversion
start
A/D conversion
result register
(ADCR) read
operation
A/D converter
sampling time
and A/D
conversion start
delay time
Register
generating wait
cycle
UART mode
REF
Details of
Function
pin input
In this A/D converter, the internal sampling capacitor is charged and sampling is
performed for approx. one sixth of the conversion time.
Since only the leakage current flows other than during sampling and the current
for charging the capacitor also flows during sampling, the input impedance
fluctuates and has no meaning.
To perform sufficient sampling, however, it is recommended to make the output
impedance of the analog input source 10 kΩ or lower, or connect a capacitor of
around 100 pF to the ANI0 to ANI7 pins (see Figure 12-19).
A series resistor string of several tens of kΩ is connected between the AV
AV
Therefore, if the output impedance of the reference voltage source is high, this
will result in a series connection to the series resistor string between the AV
and AV
The interrupt request flag (ADIF) is not cleared even if the analog input channel
specification register (ADS) is changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D
conversion result and ADIF for the pre-change analog input may be set just
before the ADS rewrite. Caution is therefore required since, at this time, when
ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D
conversion for the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D
conversion operation is resumed.
The first A/D conversion value immediately after A/D conversion starts may not
fall within the rating range if the ADCS bit is set to 1 within 14
bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take
measures such as polling the A/D conversion end interrupt request (INTAD) and
removing the first conversion result.
When a write operation is performed to the A/D converter mode register (ADM)
and analog input channel specification register (ADS), the contents of ADCR may
become undefined. Read the conversion result following conversion completion
before writing to ADM and ADS. Using a timing other than the above may cause
an incorrect conversion result to be read.
The A/D converter sampling time differs depending on the set value of the A/D
converter mode register (ADM).
The delay time exists until actual sampling is started after A/D converter operation
is enabled.
When using a set in which the A/D conversion time must be strictly observed,
care is required for the contents shown in Figure 12-21 and Table 12-3.
Do not read data from the ADCR register and do not write data to the ADM, ADS,
PFM, and PFT registers while the CPU is operating on the subsystem clock and
while high-speed system clock oscillation is stopped.
If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode),
normal operation continues. If clock supply to serial interface UART0 is stopped
(e.g., in the STOP mode), each register stops operating, and holds the value
immediately before clock supply was stopped. The TxD0 pin also holds the value
immediately before clock supply was stopped and outputs it. However, the
operation is not guaranteed after clock supply is resumed. Therefore, reset the
circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.
Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception)
to start communication.
SS
pins.
SS
APPENDIX D LIST OF CAUTIONS
pins, resulting in a large reference voltage error.
User’s Manual U16962EJ3V0UD
Cautions
µ
s after the ADCE
REF
REF
and
p. 243
p. 243
p. 244
p. 244
p. 244
p. 245
p. 245
p. 247
p. 247
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