upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 492

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

492
Serial
interface
UART6
Function
ASIM6:
Asynchronous
serial interface
operation mode
register 6
ASIS6:
Asynchronous
serial interface
reception error
status register 6
ASIF6:
Asynchronous
serial interface
transmission
status register 6
CKSR6: Clock
selection
register 6
BRGC6: Baud
rate generator
control register
6
ASICL6:
Asynchronous
serial interface
control register
6
Details of
Function
At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation,
clear TXE6 to 0, and then clear POWER6 to 0.
At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation,
clear RXE6 to 0, and then clear POWER6 to 0.
Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6
pin. If POWER6 is set to 1 and RXE6 is set to 1 while a low level is input,
reception is started.
Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
Fix the PS61 and PS60 bits to 0 when UART6 is used in the LIN communication
operation.
Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always
performed with “the number of stop bits = 1”, and therefore, is not affected by the
set value of the SL6 bit.
Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
The operation of the PE6 bit differs depending on the set values of the PS61 and
PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6).
The first bit of the receive data is checked as the stop bit, regardless of the
number of stop bits.
If an overrun error occurs, the next receive data is not written to receive buffer
register 6 (RXB6) but discarded.
If data is read from ASIS6, a wait cycle is generated. Do not read data from
ASIS6 when the CPU is operating on the subsystem clock and the high-speed
system clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
To transmit data continuously, write the first transmit data (first byte) to the TXB6
register. After that, be sure to check that the TXBF6 flag is “0”. If so, write the
next transmit data (second byte) to the TXB6 register. If data is written to the
TXB6 register while the TXBF6 flag is “1”, the transmit data cannot be
guaranteed.
To initialize the transmission unit upon completion of continuous transmission, be
sure to check that the TXSF6 flag is “0” after generation of the transmission
completion interrupt, and then execute initialization. If initialization is executed
while the TXSF6 flag is “1”, the transmit data cannot be guaranteed.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the base clock is the internal oscillation clock, the operation of serial interface
UART6 is not guaranteed.
Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when
rewriting the MDL67 to MDL60 bits.
The baud rate is the output clock of the 8-bit counter divided by 2.
ASICL6 can be refreshed (the same value is written) by software during a
communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1
or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Note, however, that
communication is started by the refresh operation because bit 6 (SBRT6) of
ASICL6 is cleared to 0 when communication is completed (when an interrupt
signal is generated).
In the case of an SBF reception error, return the mode to the SBF reception
mode. The status of the SBRF6 flag is held (1).
APPENDIX D LIST OF CAUTIONS
User’s Manual U16962EJ3V0UD
Cautions
p. 276
p. 276
p. 276
p. 276
p. 276
p. 276
p. 276
p. 277
p. 277
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p. 279
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