ad6435 Analog Devices, Inc., ad6435 Datasheet - Page 6

• Manufacturer Part Number: ad6435
• Description: Adsl Shipset
• Manufacturer: Analog Devices, Inc.

This Material Copyrighted By Its Respective Manufacturer
AD6435
INTRODUCTION
The AD6435 is the interface chip in the AD20msp910 ADSL
chipset, connecting the core transceiver functions to the external
system. The other portions within the AD20msp910 chipset are
the AD6436 (which connects to the AD6435 and is responsible
for the core DMT signal processing), the AD6437 analog front-
end IC, the AD816 driver/receiver and ADTSP2183, which is
used as the system control processor. An object code licence for
all modem software is supplied with the AD20msp910 chipset.
The AD6435 implements a generic interface, with straightfor-
ward synchronous clock and data streams corresponding to
simplex and duplex bearer channels. These can be considered as
the AS0 (simplex) and LS0 (duplex) streams as per the standard,
but can run at any rate; the “duplex” channel can be treated as
two independent streams, one up and one down. This implemen-
tation is a simplified variant of that described in ANSI T1.413.
It is easy to use this structure to connect to the rest of the sys-
tem, or to external devices, such as framers or dedicated ICs for
particular protocols. Variants of the AD6435 with support for
specific functions or interfaces (e.g., ATM, Ethernet) are under
development.
There are two main blocks within the AD6435:
• The digital processing section (Digital Interface Area or
• The interface block (Transceiver Interface and Control Logic
This data sheet gives a user’s description of the AD6435. It
describes functionality and interfacing, but does not give any
details of the internal structure. For details of the internal struc-
ture, see the AD6435 User’s Manual, available on request.
“DIA”), which is responsible for error correction, scram-
bling, interleaving, AOC and control operations. This is
based on the earlier AD6442 device. This is a highly pro-
grammable system, whose operation is not restricted to the
operating modes as defined in ANSI T1.413, but which
could be used in variety of systems. The DIA supports the
following codeword cases:
a. One codeword per frame in the fact and/or interleaved
b. Multiple codewords per frame in the fast and/or inter-
c. Multiple frames per codeword on the interleaved portion
d. Codewords may span superframes.
or “TICL”), which handles the framing, signal buffering and
data retiming functions required to support clean synchronous
data streams. (This essentially corresponds to the transmission
convergence layer of a stack.) As some designs may not require
the TICL block, there is a bypass mode, in which this block is
powered down and there is access to the unformatted/unframed
data stream from the DIA.
data portion of a frame.
leaved data portion, providing the codeword length evenly
divides into the output (DME) frame length.
of the frame only, up to 20 frames per codeword. The
number of checkbytes must be an integer multiple of the
number of frames in the codeword.
–6–
When used as part of the AD20msp910 ADSL chipset, the
internal functionality is under the control of the firmware sup-
plied with the ADTSP2183, and the Messaging Protocol (MP)
implemented there. This protocol supplies a hardware-neutral
method of controlling the operation of the ADSL chipset, which
will be compatible between different hardware implementations.
The AD6435 can implement rate adaptive ADSL (RADSL).
This is under the control of the MP, and several different modes
are supported.
The absolute maximum data rate of the AD6435 is 12 Mbps
downstream, and 4 Mbps upstream. However, the rate depends
primarily on the channel conditions, and these rates will not be
achieved on real loops, with attenuation and crosstalk.
INTERFACES
The standard interface is a very straightforward buffered and
demultiplexed synchronous connection. It is physically the same
at both ATU-R and ATU-C, and presents four channels—
simplex in and out, duplex in and out—with just two signals per
connection, clock and data (obviously, only three of these chan-
nels can be used at an end; with the ATU-C using simplex_in
and the ATU-R simplex_out). These streams are independent
and can be used asynchronously of one another. No framing
signals are provided.
The “duplex” stream can be used as a true duplex carrier (same
rates upstream and downstream) or the two may be independent
(i.e., the chipset has two simplex downstream paths, one fast
and one slower, and one simplex upstream).
Figure 1. Functional Diagram
RX_BUF
RFS
RX_FR
RX_SPFR
RX_SPFRI
TX_BUF
TX_FR
TFS
TX_SPFR
MCLK_OUT
DUPLX_RX
DUPLX_CLKO
DUPLX_CLKI
DUPLX_TX
SIMPLX_CLKI
SIMPLX_TX
SIMPLX_CLKO
SIMPLX_RX
CONTROL INTERFACE
ADTSP2183 INTERFACE
DTIR
TX_RX_SCLK
RX_SDATA
TX_SDATA
RX_DREQ
M_A(14:0)
TX_DREQ
M_D(7:0)
RX_FRM
TX_FRM
NM_WE
NM_OE
RX_BS
TX_BS
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