ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 14

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Table 6-2. Output Clock Pin Descriptions
Rev: 012108
____________________________________________________________________________________________ DS3102
PIN NAME
OC4POS,
OC5POS,
OC6POS,
OC7POS,
OC4NEG
OC5NEG
OC6NEG
OC7NEG
MFSYNC
FSYNC
GPIO1
GPIO2
GPIO3
OC1B/
OC2B/
OC3B/
OC4B
OC5B
OC1
OC2
OC3
OC4
OC5
(1)
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
DIFF
DIFF
DIFF
DIFF
3
3
3
3
3
3
3
(2)
Output Clock 1. CMOS/TTL. Programmable frequency (default 25MHz).
Output Clock 2. CMOS/TTL. Programmable frequency (default 62.5MHz).
Output Clock 3. CMOS/TTL. Programmable frequency (default 77.76MHz).
Output Clock 4. CMOS/TTL. Programmable frequency (default 125MHz).
Output Clock 5. CMOS/TTL. Programmable frequency (default 155.52MHz).
Output Clock 4. LVDS/LVPECL. These pins present the same clock as the OC4 pin but in
differential signal format. The output mode is selected by MCR8.OC4SF[1:0]. See
Table
Output Clock 5. LVDS/LVPECL. These pins present the same clock as the OC5 pin but in
differential signal format. The output mode is selected by MCR8.OC5SF[1:0]. See
Table
Output Clock 6. LVDS/LVPECL. Programmable frequency (default 156.25MHz LVDS). The
output mode is selected by MCR8.OC6SF[1:0]. See
Figure 10-3.
Output Clock 7. LVDS/LVPECL. Programmable frequency (default 312.5MHz LVDS). The
output mode is selected by MCR8.OC7SF[1:0]. See
Figure 10-3.
Output Clock 1B/General-Purpose I/O 1. CMOS/TTL (default CLK1B, disabled). This pin is
programmable as an output clock pin or a GPIO pin using OCR6.OC1BEN. When programmed
as a clock output pin (OC1BEN = 1) it presents the same clock as the OC1 pin. This pin is
powered from the V
Output Clock 2B/General-Purpose I/O 2. CMOS/TTL (default CLK2B, disabled). This pin is
programmable as an output clock pin or a GPIO pin using OCR6.OC2BEN. When programmed
as a clock output pin (OC2BEN = 1) it presents the same clock as the OC2 pin. This pin is
powered from the V
Output Clock 3B/General-Purpose I/O 3. CMOS/TTL (default CLK3B, disabled). This pin is
programmable as an output clock pin or a GPIO pin using OCR6.OC3BEN. When programmed
as a clock output pin (OC3BEN = 1) it presents the same clock as the OC3 pin. This pin is
powered from the V
Output Clock 4B. CMOS/TTL (default off). When enabled (OCR6.OC4BEN = 1), this pin
presents the same clock as the OC4 pin. This pin is powered from the V
Output Clock 5B. CMOS/TTL (default off) . When enabled (OCR6.OC5BEN = 1), this pin
presents the same clock as the OC5 pin. This pin is powered from the V
FSYNC. CMOS/TTL. 8kHz frame sync or clock (default 50% duty cycle clock, noninverted). The
pulse polarity and width are selectable using FSCR1.8KINV and FSCR1.8KPUL.
MFSYNC. CMOS/TTL. 2kHz frame sync or clock (default 50% duty cycle clock, noninverted).
The pulse polarity and width are selectable using FSCR1.2KINV and FSCR1.2KPUL.
10-6,
10-6,
Figure
Figure
10-1, and
10-1, and
DDIOB
DDIOB
DDIOB
power-supply pin.
power-supply pin.
power-supply pin.
Figure 10-3.
Figure 10-3.
PIN DESCRIPTION
Table
Table
10-5,
10-5,
Table
Table
10-6,
10-6,
DDIOB
DDIOB
Figure
Figure
power-supply pin.
power-supply pin.
Table
Table
10-1, and
10-1, and
14 of 141
10-5,
10-5,