ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 94

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Frequency Limit Loss-of-Lock (FLLOL). When this bit is set to 1, the T0 DPLL and the T4 DPLL internally
declare loss-of-lock when their hard limits are reached. The T0 DPLL hard frequency limit is set in the
HARDLIM[9:0] field in the
See Section 7.7.6.
Bits 6 to 0: DPLL Soft Frequency Limit (SOFTLIM[6:0]). This field is an unsigned integer that specifies the soft
frequency limit for the T0 DPLL and the T4 DPLL. The soft limit is only used for monitoring; exceeding this limit
does not cause loss-of-lock. The limit in ppm is ±SOFTLIM[6:0] × 0.628. The default value is ±8.79ppm. When the
T0 DPLL frequency reaches the soft limit the T0SOFT status bit is set in the
DPLL frequency reaches the soft limit the T4SOFT status bit is set in OPSTATE. See Section 7.7.6.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Interrupt Enable for Fast Holdover Frequency Ready (FHORDY). This bit is an interrupt enable for the
FHORDY bit in the
Bit 6: Interrupt Enable for Slow Holdover Frequency Ready (SHORDY). This bit is an interrupt enable for the
SHORDY bit in the
Rev: 012108
____________________________________________________________________________________________ DS3102
0 = DPLL declares loss-of-lock normally.
1 = DPLL also declares loss-of-lock when the hard frequency limit is reached.
0 = Mask the interrupt
1 = Enable the interrupt
0 = Mask the interrupt
1 = Enable the interrupt
FHORDY
FLLOL
7
1
7
0
MSR4
MSR4
register.
register.
DLIMIT1
SHORDY
6
0
6
0
DLIMIT3
DPLL Frequency Limit Register 3
4Dh
IER4
Interrupt Enable Register 4
4Eh
and
DLIMIT2
—
5
0
5
0
registers. The T4 DPLL hard frequency limit is fixed at ±80ppm.
4
0
—
4
0
SOFTLIM[6:0]
3
1
—
3
0
OPSTATE
—
2
1
2
0
register. When the T4
—
1
0
1
1
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—
0
0
0
0