ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 20

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

7.4.2 Frequency Configuration
Input clock frequencies are configured in the FREQ field of the
same registers specify the locking frequency mode, as shown in
Table 7-3. Locking Frequency Modes
7.4.2.1 Direct Lock Mode
In direct lock mode, the DPLLs lock to the selected reference at the frequency specified in the corresponding
register. Direct lock mode can only be used for input clocks with these specific frequencies: 2kHz, 4kHz, 8kHz,
1.544MHz, 2.048MHz, 5MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.92MHz, 31.25MHz, 38.88MHz, 51.84MHz,
77.76MHz, and 155.52MHz. For the 155.52MHz case, the input clock is internally divided by two, and the DPLL
direct-locks at 77.76MHz. The DIVN mode can be used to divide an input down to any of these frequencies except
155.52MHz.
MTIE figures may be marginally better in direct lock mode because the higher frequencies allow more frequent
phase updates.
7.4.2.2 Alternate Direct Lock Mode
Alternate direct lock mode is the same as direct lock mode except an alternate list of direct lock frequencies is used
(see the FREQ field definition in the
clock rates found in Ethernet, CMTS, wireless, and GPS applications. The alternate frequencies are: 10MHz,
25MHz, 62.5MHz, 125MHz, and 156.25MHz. The frequencies 62.5MHz, 125MHz, and 156.25MHz are internally
divided down to 31.25MHz, while 10MHz and 25MHz are internally divided down to 5MHz.
7.4.2.3 LOCK8K Mode
In LOCK8K mode, an internal divider is configured to divide the selected reference down to 8kHz. The DPLL locks
to the 8kHz output of the divider. LOCK8K mode can only be used for input clocks with the standard direct lock
frequencies: 8kHz, 1.544MHz, 2.048MHz, 5MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.0MHz, 25.92MHz,
31.25MHz, 38.88MHz, 51.84MHz, 62.5MHz, 77.76MHz, and 155.52MHz. LOCK8K mode is enabled for a particular
input clock by setting the LOCK8K bit in the corresponding
LOCK8K mode gives a greater tolerance to input jitter when the multicycle phase detector is disabled because it
uses lower frequencies for phase comparisons. The clock edge to lock to on the selected reference can be
configured using the 8KPOL bit in the
direct-lock mode is used.
7.4.2.4 DIVN Mode
In DIVN mode, an internal divider is configured from the value stored in the
be chosen so that when the selected reference is divided by DIVN + 1, the resulting clock frequency is the same as
the standard direct lock frequency selected in the FREQ field of the
the divider. DIVN mode can only be used for input clocks whose frequency is less than or equal to 155.52MHz. The
DIVN register field can range from 0 to 65,535 inclusive. The same DIVN + 1 factor is used for all input clocks
configured for DIVN mode. Note that although the DIVN divider is able to divide down clock rates as high as
155.52MHz, the CMOS/TTL inputs are only rated for a maximum clock rate of 125MHz.
Rev: 012108
____________________________________________________________________________________________ DS3102
DIVN
0
0
1
1
LOCK8K
0
1
0
1
Direct Lock
LOCK8K
DIVN
Alternate Direct Lock
LOCKING FREQUENCY
MODE
ICR
TEST1
register description). The alternate frequencies are included to support
register. For 2kHz and 4kHz clocks the LOCK8K bit is ignored and
ICR
ICR
register.
Table
registers. The DIVN and LOCK8K bits of these
ICR
7-3.
register. The DPLL locks to the output of
DIVN
registers. The DIVN value must
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ICR