ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 4

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

____________________________________________________________________________________________ DS3102
List of Figures
Figure 2-1. Typical Application Example ..................................................................................................................... 7
Figure 3-1. Block Diagram ........................................................................................................................................... 8
Figure 7-1. DPLL Block Diagram ............................................................................................................................... 26
Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 28
Figure 7-3. T4 DPLL State Transition Diagram ......................................................................................................... 31
Figure 7-4. FSYNC 8kHz Options.............................................................................................................................. 44
Figure 7-5. SPI Clock Phase Options ........................................................................................................................ 50
Figure 7-6. SPI Bus Transactions.............................................................................................................................. 51
Figure 9-1. JTAG Block Diagram............................................................................................................................. 123
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 125
Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 130
Figure 10-2. Recommended Termination for LVPECL Signals on LVDS Input Pins .............................................. 130
Figure 10-3. Recommended Termination for LVPECL-Compatible Output Pins .................................................... 131
Figure 10-4. SPI Interface Timing Diagram ............................................................................................................. 134
Figure 10-5. JTAG Timing Diagram......................................................................................................................... 135
Figure 10-6. Reset Pin Timing Diagram .................................................................................................................. 136
Figure 11-1. Pin Assignment Diagram..................................................................................................................... 138
Rev: 012108
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