ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 36

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Table 7-6. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode
Note 1: In this case the T0 select reference must be the same frequency as the T4 selected reference.
Note 2: If the T4 selected reference frequency is 8kHz and the T0 selected reference is a different frequency, the two references can be
compared by configuring the T4 selected reference for 8kHz and LOCK8K mode. This forces the copy of the T0 selected reference to be divided
down to 8kHz using either LOCK8K or DIVN mode.
Note 3: DIVN(8K) means that the FREQ field is set to 8kHz, DIVN(not 8K) means the FREQ field is not set to 8kHz.
7.7.11 Input Jitter and Wander Tolerance
The device is compliant with the jitter and wander tolerance requirements of the standards listed in
Wander can be tolerated up to the point where wander causes an apparent long-term frequency offset larger than
the limits specified in the
invalid. When using the ±360°/±180° PFD, jitter can be tolerated up to the point of eye closure. Either LOCK8K
mode (see Section 7.4.2.3) or the multicycle phase detector (see Section 7.7.5) should be used for high jitter
tolerance.
7.7.12 Jitter and Wander Transfer
The transfer of jitter and wander from the selected reference to the output clocks has a programmable transfer
function that is determined by the DPLL bandwidth. (See Section 7.7.3.) In the T0 DPLL, the 3dB corner frequency
of the jitter transfer function can be set to any of 21 positions from 0.5mHz to 400Hz. In the T4 DPLL the 3dB
corner frequency of the jitter transfer function can be set to various values from 18Hz to 70Hz.
During locked mode, the transfer of wander from the local oscillator clock (connected to the REFCLK pin) to the
output clocks is not significant as long as the DPLL bandwidth is set high enough to allow the DPLL to quickly
compensate for oscillator frequency changes. During free-run and holdover modes, local oscillator wander has a
much more significant effect. See Section 7.3.
Rev: 012108
____________________________________________________________________________________________ DS3102
LOCKING MODE
REFERENCE
DIVN (not 8K)
SELECTED
LOCK8K or
LOCK8K or
LOCK8K or
LOCK8K or
DIVN(8K)
DIVN(8K)
DIVN(8K)
DIVN(8K)
DIRECT
FOR T4
MODE FOR T0
DIVN (not 8K)
REFERENCE
SELECTED
LOCKING
DIVN (8K)
LOCK8K
DIRECT
ILIMIT
Any
Any
and/or
SRLIMIT
REFERENCE
COPY OF T0
MODE FOR
SELECTED
LOCKING
LOCK8K
LOCK8K
DIRECT
DIRECT
DIRECT
DIVN
registers. In such a situation the input clock would be declared
FREQUENCY OF THE
Same as the T4 forced
Same as the T4 forced
REFERENCE FOR
MEASUREMENT
T4MT0 PHASE
T4 SELECTED
reference input
reference input
frequency
frequency
8kHz
8kHz
8kHz
8kHz
Same as the T0 selected
Same as the T0 selected
FREQUENCY OF THE
REFERENCE FOR
MEASUREMENT
T4MT0 PHASE
T0 SELECTED
reference input
reference input
frequency
frequency
8kHz
8kHz
8kHz
8kHz
Table
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