cs8952t Cirrus Logic, Inc., cs8952t Datasheet - Page 41

• Manufacturer Part Number: cs8952t
• Description: 100base 10base-t Transceiver
• Manufacturer: Cirrus Logic, Inc.

Interrupt Mask Register - Address 10h
This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as an enable to the interrupt.
Thus, when set, the event will cause the MII_IRQ pin to be asserted. When clear, the event will not affect the MII_IRQ pin, but
the status will still be reported via the Interrupt Status Register (address 11h).
DS206TPP2
15
14
13
12
CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
BIT
Complete
CIM Link
Unstable
Reset
15
7
CIM Link Unstable
Link Status Change Read/Write 1
Descrambler Lock
Change
Premature End
Error
NAME
Link Status
Change
Jabber
Detect
14
6
Read/Write 0
Read/Write 0
Read/Write 0
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Lock Change
Descrambler
Auto-Neg
Complete
TYPE
13
5
Premature
End Error
Detection
Parallel
RESET
Fault
12
4
Rollover
Parallel
When set, an interrupt will be generated if an unsta-
ble link condition is detected by the Carrier Integrity
Monitor function.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated each time
the CS8952T detects a change in the link status.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated each time
the 100BASE-TX receive descrambler loses or
regains synchronization with the far-end.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated when two
consecutive IDLES are detected in a 100BASE-TX
frame without the End-of-Stream-Delimiter sequence.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
DCR
Fail
11
3
Rollover
Remote
FCCR
Fault
10
2
DESCRIPTION
Received
Rollover
RECR
Page
9
1
Loopback
Reserved
Remote
Fault
8
0
41