cs8952t Cirrus Logic, Inc., cs8952t Datasheet - Page 42
cs8952t
Manufacturer Part Number
cs8952t
Description
100base 10base-t Transceiver
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CS8952T.pdf
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Interrupt Mask Register - Address 10h (Cont.)
42
11
10
9
8
7
6
BIT
DCR Rollover
FCCR Rollover
RECR Rollover
Remote Loopback
Fault
Reset Complete
Jabber Detect
NAME
Read/Write 0
Read/Write 0
Read/Write 0
Read/Write 0
Read/Write 1
Read/Write 0
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
TYPE
RESET
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
When set, an interrupt will be generated if the MSB in
the DCR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the MSB in
the FCCR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the MSB in
the RECR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the elastic
buffer in the PMA is under-run or over-run during
Remote Loopback. This should not occur for normal
length 802.3 frames.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated once the dig-
ital and analog sections have been reset, and a cali-
bration cycle has been performed.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated when a Jab-
ber condition is detected by the 10BASE-T MAU.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
DESCRIPTION
DS206TPP2
CS8952T
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