cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 48

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

2.26.2.3 Enforcing Minimum Frame Size
The MAC provides minimum frame size enforce-
ment of both transmit and receive packets. When
the TxPadDis bit (TxCMD register, Bit D) is clear,
transmit frames will be padded with additional bits
to ensure that the receiving station receives a legal
frame (64 bytes, including CRC). When TxPadDis
is set, the Ethernet port will not add pad bits and
will transmit frames less that 64 bytes. If a frame is
received that is less than 64 bytes (including CRC),
the Runt bit (RxEvent register, Bit D) will be set in-
dicating the arrival of an illegal frame.
2.26.3 Transmit Error Detection/Handling
The MAC engine monitors Ethernet activity and
reports and recovers from a number of error condi-
tions. For transmission, the MAC reports the fol-
lowing errors in TxEvent (Register 8) and
BufEvent (Register C):
2.26.3.1 Out-of-Window (Late) Collision
If a collision is detected after the first 512 bits have
been transmitted, the MAC reports a late collision
by setting the Out-of-window bit (TxEvent regis-
ter, Bit 9). The MAC then forces a bad CRC and
terminates the transmission. If the Out-of-window-
iE bit (TxCFG register, Bit 9) is set, an interrupt is
generated. A late collision may indicate an illegal
network configuration.
2.26.3.2 Jabber Error
If a transmission continues longer than about
26 ms, the MAC disables the transmitter and sets
the Jabber bit (TxEvent register, Bit A). The output
of the transmitter returns to idle and remains there
until the software issues a new Transmit Com-
mand. If the JabberiE bit (TxCFG register, Bit A) is
set, an interrupt is generated. A Jabber condition in-
dicates a possible error in the Ethernet port transmit
function. To prevent possible network faults, the
48
software should clear the transmit buffer. Possible
options include:
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2.26.3.3 Transmit Collision
The MAC counts the number of times an individual
packet must be retransmitted due to network colli-
sions. The collision count is stored in bits B
through E of the TxEvent register. If the packet col-
lides 16 times, transmission of that packet is termi-
nated and the 16coll bit (TxEvent register, Bit F) is
set. If the 16colliE bit (TxCFG register, Bit F) is
set, an interrupt is generated on the 16th collision.
A running count of transmit collisions is recorded
in the TxCOL register.
2.26.3.4 Transmit Underrun
If the Ethernet port starts transmission of a packet
but runs out of data before reaching the end of
frame, the TxUnderrun bit (BufEvent register, Bit
9) is set. The MAC then forces a bad CRC and ter-
minates the transmission. If the TxUnderruniE bit
(BufCFG bit 9) is set, an interrupt is generated.
2.26.4 Receive Error Detection/Handling
The following receive errors are reported in the Rx-
Event register:
2.26.4.1 CRC Error
If a frame is received with a bad CRC, the CRCer-
ror bit (RxEvent register, Bit C) is set. If the
CRCerrorA bit (RxCTL register, Bit C) is set, the
frame will be buffered by Ethernet port. If the
CRCerroriE bit (RxCFG register. Bit C) is set, an
interrupt is generated.
Reset the chip with either software or hardware
reset (see Section 2.24, “Programming the EE-
PROM”).
Issue a Force Transmit Command by setting the
Force bit (TxCMD register, bit 8).
Issue a Transmit Command with the TxLength
field set to zero.
CS89712
DS502PP2