cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 90

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

3.6.2
This interrupt mask register is a 32-bit read / write register, which is used to selectively enable any of the first 16
interrupt sources within the CS89712. The four shaded interrupts all generate a fast interrupt request to the
ARM720T processor (FIQ), this will cause a jump to processor virtual address 0000.0001C. All other interrupts will
generate a standard interrupt request (IRQ), this will cause a jump to processor virtual address 0000.00018. Setting
the appropriate bit in this register enables the corresponding interrupt. All bits are cleared by a system reset. Please
refer to Section 3.6, “Interrupt Registers” for individual bit details.
90
9
10
11
12
13
14
15
Bit
SSEOTI
EINT3
15
7
INTMR1 Interrupt Mask Register 1 (address 0x8000.0280)
TC2OI: TC2 under flow interrupt. This interrupt becomes active on the next falling edge of the timer
counter 2 clock after the timer counter has under flowed (reached zero). It is cleared by writing to the
TC2EOI location.
RTCMI: RTC compare match interrupt. This interrupt becomes active on the next rising edge of the
1 Hz Real-Time Clock (one second later) after the 32-bit time written to the Real-Time Clock match reg-
ister exactly matches the current time in the RTC. It is cleared by writing to the RTCEOI location.
TINT: 64 Hz tick interrupt. This interrupt becomes active on every rising edge of the internal
64 Hz clock signal. This 64 Hz clock is derived from the 15-stage ripple counter that divides the
32.768 kHz oscillator input down to 1 Hz for the Real-Time Clock. This interrupt is cleared by writing to
the TEOI location.
Note: TINT is disabled / turned off during Snooze/the Standby States.
UTXINT1: Internal UART1 transmit FIFO half-empty interrupt. The function of this interrupt source
depends on whether the UART1 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the
UART1 bit rate and line control register), this interrupt will be active when there is no data in the UART1
TX data holding register and be cleared by writing to the UART1 data register. If the FIFO is enabled
this interrupt will be active when the UART1 TX FIFO is half or more empty, and is cleared by filling the
FIFO to at least half full.
URXINT1: Internal UART1 receive FIFO half full interrupt. The function of this interrupt source depends
on whether the UART1 FIFO is enabled. If the FIFO is disabled this interrupt will be active when there is
valid RX data in the UART1 RX data holding register and be cleared by reading this data. If the FIFO is
enabled this interrupt will be active when the UART1 RX FIFO is half or more full or if the FIFO is non
empty and no more characters have been received for a three character time out period. It is cleared by
reading all the data from the RX FIFO.
UMSINT: Internal UART1 modem status changed interrupt. This interrupt will be active if either of the
two modem status lines (CTS or DSR) change state. It is cleared by writing to the UMSEOI location.
SSEOTI: Synchronous serial interface end of transfer interrupt. This interrupt will be active after a com-
plete data transfer to and from the external ADC has been completed. It is cleared by reading the ADC
data from the SYNCIO register.
UMSINT
EINT2
14
6
URXINT
EINT1
13
5
Table 42. INTSR1 (Continued)
UTXINT
CSINT
12
4
Description
MCINT
TINT
11
3
WEINT
RTCMI
10
2
TC2OI
BLINT
1
9
CS89712
DS502PP2
EXTFIQ
TC1OI
8
0